01d1eb4258
Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
313 lines
8.7 KiB
C
313 lines
8.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "spl-x1000.h"
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#include "spl-target.h"
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#include "clk-x1000.h"
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#include "nand-x1000.h"
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#include "system.h"
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#include "x1000/cpm.h"
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#include "x1000/ost.h"
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#include "x1000/ddrc.h"
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#include "x1000/ddrc_apb.h"
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#include "x1000/ddrphy.h"
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struct x1000_spl_arguments* const spl_arguments =
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(struct x1000_spl_arguments*)SPL_ARGUMENTS_ADDRESS;
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struct x1000_spl_status* const spl_status =
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(struct x1000_spl_status*)SPL_STATUS_ADDRESS;
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/* defined to be Linux compatible; Rockbox needs no arguments so there
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* is no harm in passing them and we save a little code size */
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typedef void(*entry_fn)(int, char**, int, int);
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/* Note: This is based purely on disassembly of the SPL from the FiiO M3K.
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* The code there is somewhat generic and corresponds roughly to Ingenic's
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* U-Boot code, but isn't entirely the same.
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*
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* I converted all the runtime conditionals to compile-time ones in order to
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* save code space, since they should be constant for any given target.
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*
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* I haven't bothered to decode all the register fields. Some of the values
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* written are going to bits documented as "Reserved" by Ingenic, but their
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* documentation doesn't seem completely reliable, so either these are bits
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* which _do_ have a purpose, or they're only defined on other Ingenic CPUs.
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*
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* The DDR PHY registers appear to be from Synopsys "PHY Utility Block Lite".
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* These aren't documented by Ingenic, but the addresses and names can be found
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* in their U-Boot code.
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*/
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static void ddr_init(void)
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{
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REG_CPM_DRCG = 0x73;
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mdelay(3);
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REG_CPM_DRCG = 0x71;
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mdelay(3);
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REG_DDRC_APB_PHYRST_CFG = 0x1a00001;
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mdelay(3);
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REG_DDRC_APB_PHYRST_CFG = 0;
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mdelay(3);
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REG_DDRC_CTRL = 0xf00000;
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mdelay(3);
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REG_DDRC_CTRL = 0;
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mdelay(3);
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REG_DDRC_CFG = 0xa468a6c;
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REG_DDRC_CTRL = 2;
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REG_DDRPHY_DTAR = 0x150000;
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REG_DDRPHY_DCR = 0;
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REG_DDRPHY_MR0 = 0x42;
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REG_DDRPHY_MR2 = 0x98;
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REG_DDRPHY_PTR0 = 0x21000a;
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REG_DDRPHY_PTR1 = 0xa09c40;
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REG_DDRPHY_PTR2 = 0x280014;
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REG_DDRPHY_DTPR0 = 0x1a69444a;
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REG_DDRPHY_DTPR1 = 0x180090;
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REG_DDRPHY_DTPR2 = 0x1ff99428;
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REG_DDRPHY_DXGCR(0) = 0x90881;
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REG_DDRPHY_DXGCR(1) = 0x90881;
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REG_DDRPHY_DXGCR(2) = 0x90e80;
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REG_DDRPHY_DXGCR(3) = 0x90e80;
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REG_DDRPHY_PGCR = 0x1042e03;
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REG_DDRPHY_ACIOCR = 0x30c00813;
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REG_DDRPHY_DXCCR = 0x4912;
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int i = 10000;
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while(i > 0 && REG_DDRPHY_PGSR != 7 && REG_DDRPHY_PGSR != 0x1f)
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i -= 1;
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if(i == 0)
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spl_error();
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#if SPL_DDR_NEED_BYPASS
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REG_DDRPHY_ACDLLCR = 0x80000000;
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REG_DDRPHY_DSGCR &= ~0x10;
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REG_DDRPHY_DLLGCR |= 0x800000;
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REG_DDRPHY_PIR = 0x20020041;
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#else
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REG_DDRPHY_PIR = 0x41;
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#endif
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while(i > 0 && REG_DDRPHY_PGSR != 0xf && REG_DDRPHY_PGSR != 0x1f)
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i -= 1;
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if(i == 0)
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spl_error();
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REG_DDRC_APB_PHYRST_CFG = 0x400000;
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mdelay(3);
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REG_DDRC_APB_PHYRST_CFG = 0;
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mdelay(3);
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REG_DDRC_CFG = 0xa468aec;
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REG_DDRC_CTRL = 2;
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#if SPL_DDR_NEED_BYPASS
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REG_DDRPHY_PIR = 0x20020081;
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#else
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REG_DDRPHY_PIR = 0x85;
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#endif
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i = 500000;
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while(REG_DDRPHY_PGSR != 0x1f) {
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if(REG_DDRPHY_PGSR & 0x70)
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break;
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i -= 1;
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}
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if(i == 0)
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spl_error();
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if((REG_DDRPHY_PGSR & 0x60) != 0 && REG_DDRPHY_PGSR != 0)
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spl_error();
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REG_DDRC_CTRL = 0;
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REG_DDRC_CTRL = 10;
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REG_DDRC_CTRL = 0;
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REG_DDRC_CFG = 0xa468a6c;
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REG_DDRC_TIMING1 = 0x2050501;
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REG_DDRC_TIMING2 = 0x4090404;
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REG_DDRC_TIMING3 = 0x2704030d;
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REG_DDRC_TIMING4 = 0xb7a0251;
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REG_DDRC_TIMING5 = 0xff090200;
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REG_DDRC_TIMING6 = 0xa0a0202;
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#if SPL_DDR_MEMORYSIZE == 64
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REG_DDRC_MMAP0 = 0x20fc;
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REG_DDRC_MMAP1 = 0x2400;
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#elif SPL_DDR_MEMORYSIZE == 32
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REG_DDRC_MMAP0 = 0x20fe;
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REG_DDRC_MMAP1 = 0x2200;
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#else
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# error "Unsupported DDR_MEMORYSIZE"
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#endif
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REG_DDRC_CTRL = 10;
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REG_DDRC_REFCNT = 0x2f0003;
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REG_DDRC_CTRL = 0xc91e;
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#if SPL_DDR_MEMORYSIZE == 64
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REG_DDRC_REMAP1 = 0x03020c0b;
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REG_DDRC_REMAP2 = 0x07060504;
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REG_DDRC_REMAP3 = 0x000a0908;
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REG_DDRC_REMAP4 = 0x0f0e0d01;
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REG_DDRC_REMAP5 = 0x13121110;
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#elif SPL_DDR_MEMORYSIZE == 32
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REG_DDRC_REMAP1 = 0x03020b0a;
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REG_DDRC_REMAP2 = 0x07060504;
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REG_DDRC_REMAP3 = 0x01000908;
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REG_DDRC_REMAP4 = 0x0f0e0d0c;
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REG_DDRC_REMAP5 = 0x13121110;
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#else
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# error "Unsupported DDR_MEMORYSIZE"
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#endif
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REG_DDRC_STATUS &= ~0x40;
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#if SPL_DDR_AUTOSR_EN
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#if SPL_DDR_NEED_BYPASS
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jz_writef(CPM_DDRCDR, GATE_EN(1));
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REG_DDRC_APB_CLKSTP_CFG = 0x9000000f;
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#else
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REG_DDRC_DLP = 0;
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#endif
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#endif
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REG_DDRC_AUTOSR_EN = SPL_DDR_AUTOSR_EN;
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}
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static void init(void)
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{
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/* from original firmware SPL */
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REG_CPM_PSWC0ST = 0x00;
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REG_CPM_PSWC1ST = 0x10;
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REG_CPM_PSWC2ST = 0x18;
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REG_CPM_PSWC3ST = 0x08;
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/* enable MPLL */
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#if X1000_EXCLK_FREQ == 24000000
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/* 24 * (24+1) = 600 MHz */
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jz_writef(CPM_MPCR, ENABLE(1), BS(1), PLLN(0), PLLM(24), PLLOD(0));
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#elif X1000_EXCLK_FREQ == 26000000
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/* 26 * (22+1) = 598 MHz */
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jz_writef(CPM_MPCR, ENABLE(1), BS(1), PLLN(0), PLLM(22), PLLOD(0));
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#else
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# error "unknown EXCLK frequency"
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#endif
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while(jz_readf(CPM_MPCR, ON) == 0);
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/* set DDR clock to MPLL/3 = 200 MHz */
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jz_writef(CPM_CLKGR, DDR(0));
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clk_set_ddr(X1000_CLK_MPLL, 3);
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/* start OST so we can use mdelay/udelay */
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jz_writef(CPM_CLKGR, OST(0));
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jz_writef(OST_CTRL, PRESCALE2_V(BY_4));
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jz_writef(OST_CLEAR, OST2(1));
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jz_write(OST_2CNTH, 0);
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jz_write(OST_2CNTL, 0);
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jz_setf(OST_ENABLE, OST2);
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/* init DDR memory */
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ddr_init();
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}
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static int nandread(uint32_t addr, uint32_t size, void* buffer)
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{
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int rc;
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if((rc = nand_open()))
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return rc;
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rc = nand_read_bytes(addr, size, buffer);
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nand_close();
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return rc;
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}
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static int nandwrite(uint32_t addr, uint32_t size, void* buffer)
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{
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int rc;
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if((rc = nand_open()))
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return rc;
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if((rc = nand_enable_writes(true)))
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goto _end;
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if((rc = nand_erase_bytes(addr, size)))
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goto _end1;
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rc = nand_write_bytes(addr, size, buffer);
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_end1:
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/* an error here is very unlikely, so ignore it */
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nand_enable_writes(false);
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_end:
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nand_close();
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return rc;
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}
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void main(void)
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{
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if(!(SPL_ARGUMENTS->flags & SPL_FLAG_SKIP_INIT))
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init();
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switch(SPL_ARGUMENTS->command) {
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case SPL_CMD_BOOT: {
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int option = SPL_ARGUMENTS->param1;
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if(option == SPL_BOOTOPT_CHOOSE)
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option = spl_get_boot_option();
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if(option == SPL_BOOTOPT_NONE)
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return;
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const struct spl_boot_option* opt = &spl_boot_options[option-1];
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if(nandread(opt->nand_addr, opt->nand_size, (void*)opt->load_addr))
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spl_error();
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/* Let target handle necessary pre-boot setup */
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spl_handle_pre_boot(option);
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/* Reading the Linux command line from the bootloader is handled by
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* arch/mips/xburst/core/prom.c -- see Ingenic kernel sources.
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*
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* Rockbox doesn't use arguments, but passing them does not hurt and it
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* saves an unnecessary branch.
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*/
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entry_fn entry = (entry_fn)opt->exec_addr;
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char** argv = (char**)0x80004000;
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argv[0] = 0;
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argv[1] = (char*)opt->cmdline;
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commit_discard_idcache();
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entry(2, argv, 0, 0);
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__builtin_unreachable();
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}
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case SPL_CMD_FLASH_READ:
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SPL_STATUS->err_code = nandread(SPL_ARGUMENTS->param1,
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SPL_ARGUMENTS->param2,
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(void*)SPL_BUFFER_ADDRESS);
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return;
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case SPL_CMD_FLASH_WRITE:
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SPL_STATUS->err_code = nandwrite(SPL_ARGUMENTS->param1,
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SPL_ARGUMENTS->param2,
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(void*)SPL_BUFFER_ADDRESS);
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return;
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}
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}
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