521 lines
32 KiB
C
521 lines
32 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3600:2.3.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__I2C__H__
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#define __HEADERGEN__STMP3600__I2C__H__
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#define REGS_I2C_BASE (0x80058000)
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#define REGS_I2C_VERSION "2.3.0"
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/**
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* Register: HW_I2C_CTRL0
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* Address: 0
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* SCT: yes
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*/
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#define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
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#define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
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#define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
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#define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
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#define BP_I2C_CTRL0_SFTRST 31
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#define BM_I2C_CTRL0_SFTRST 0x80000000
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#define BV_I2C_CTRL0_SFTRST__RUN 0x0
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#define BV_I2C_CTRL0_SFTRST__RESET 0x1
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#define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
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#define BP_I2C_CTRL0_CLKGATE 30
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#define BM_I2C_CTRL0_CLKGATE 0x40000000
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#define BV_I2C_CTRL0_CLKGATE__RUN 0x0
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#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1
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#define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
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#define BP_I2C_CTRL0_RUN 29
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#define BM_I2C_CTRL0_RUN 0x20000000
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#define BV_I2C_CTRL0_RUN__HALT 0x0
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#define BV_I2C_CTRL0_RUN__RUN 0x1
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#define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000)
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#define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
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#define BP_I2C_CTRL0_PRE_ACK 27
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#define BM_I2C_CTRL0_PRE_ACK 0x8000000
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#define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000)
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#define BP_I2C_CTRL0_ACKNOWLEDGE 26
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#define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000
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#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0
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#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1
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#define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000)
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#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
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#define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25
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#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000
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#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0
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#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1
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#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000)
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#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
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#define BP_I2C_CTRL0_PIO_MODE 24
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#define BM_I2C_CTRL0_PIO_MODE 0x1000000
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#define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000)
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#define BP_I2C_CTRL0_MULTI_MASTER 23
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#define BM_I2C_CTRL0_MULTI_MASTER 0x800000
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#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0
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#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1
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#define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000)
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#define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
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#define BP_I2C_CTRL0_CLOCK_HELD 22
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#define BM_I2C_CTRL0_CLOCK_HELD 0x400000
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#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0
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#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1
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#define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000)
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#define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
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#define BP_I2C_CTRL0_RETAIN_CLOCK 21
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#define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000
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#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0
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#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1
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#define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000)
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#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
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#define BP_I2C_CTRL0_POST_SEND_STOP 20
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#define BM_I2C_CTRL0_POST_SEND_STOP 0x100000
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#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0
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#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1
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#define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000)
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#define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
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#define BP_I2C_CTRL0_PRE_SEND_START 19
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#define BM_I2C_CTRL0_PRE_SEND_START 0x80000
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#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0
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#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1
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#define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000)
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#define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
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#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18
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#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000
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#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
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#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1
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#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000)
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#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
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#define BP_I2C_CTRL0_MASTER_MODE 17
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#define BM_I2C_CTRL0_MASTER_MODE 0x20000
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#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0
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#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1
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#define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000)
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#define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
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#define BP_I2C_CTRL0_DIRECTION 16
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#define BM_I2C_CTRL0_DIRECTION 0x10000
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#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0
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#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1
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#define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000)
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#define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
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#define BP_I2C_CTRL0_XFER_COUNT 0
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#define BM_I2C_CTRL0_XFER_COUNT 0xffff
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#define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_I2C_TIMING0
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* Address: 0x10
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* SCT: yes
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*/
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#define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
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#define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
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#define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
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#define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
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#define BP_I2C_TIMING0_HIGH_COUNT 16
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#define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000
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#define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000)
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#define BP_I2C_TIMING0_RCV_COUNT 0
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#define BM_I2C_TIMING0_RCV_COUNT 0x3ff
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#define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff)
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/**
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* Register: HW_I2C_TIMING1
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* Address: 0x20
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* SCT: yes
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*/
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#define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
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#define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
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#define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
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#define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
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#define BP_I2C_TIMING1_LOW_COUNT 16
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#define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000
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#define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000)
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#define BP_I2C_TIMING1_XMIT_COUNT 0
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#define BM_I2C_TIMING1_XMIT_COUNT 0x3ff
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#define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff)
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/**
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* Register: HW_I2C_TIMING2
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* Address: 0x30
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* SCT: yes
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*/
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#define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
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#define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
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#define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
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#define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
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#define BP_I2C_TIMING2_BUS_FREE 16
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#define BM_I2C_TIMING2_BUS_FREE 0x3ff0000
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#define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000)
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#define BP_I2C_TIMING2_LEADIN_COUNT 0
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#define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff
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#define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff)
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/**
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* Register: HW_I2C_CTRL1
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* Address: 0x40
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* SCT: yes
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*/
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#define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
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#define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
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#define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
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#define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
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#define BP_I2C_CTRL1_BCAST_SLAVE_EN 24
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#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000
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#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0
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#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1
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#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000)
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#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
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#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16
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#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000
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#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000)
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#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15
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#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000
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#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000)
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#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
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#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14
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#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000
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#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000)
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#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
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#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13
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#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000
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#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000)
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#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
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#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12
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#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000
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#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000)
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#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
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#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11
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#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800
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#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800)
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#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
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#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10
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#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400
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#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400)
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#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
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#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9
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#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200
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#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200)
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#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
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#define BP_I2C_CTRL1_SLAVE_IRQ_EN 8
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#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100
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#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0
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#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1
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#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100)
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#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
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#define BP_I2C_CTRL1_BUS_FREE_IRQ 7
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#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80
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#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0
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#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1
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#define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80)
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#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
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#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6
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#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
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#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0
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#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1
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#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40)
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#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
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#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5
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#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
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#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0
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#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1
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#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20)
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#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
|
|
#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4
|
|
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
|
|
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0
|
|
#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1
|
|
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10)
|
|
#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
|
|
#define BP_I2C_CTRL1_EARLY_TERM_IRQ 3
|
|
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8
|
|
#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0
|
|
#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1
|
|
#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8)
|
|
#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
|
|
#define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2
|
|
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4
|
|
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0
|
|
#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1
|
|
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4)
|
|
#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
|
|
#define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1
|
|
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2
|
|
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0
|
|
#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1
|
|
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2)
|
|
#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
|
|
#define BP_I2C_CTRL1_SLAVE_IRQ 0
|
|
#define BM_I2C_CTRL1_SLAVE_IRQ 0x1
|
|
#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0
|
|
#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1
|
|
#define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1)
|
|
#define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_I2C_STAT
|
|
* Address: 0x50
|
|
* SCT: no
|
|
*/
|
|
#define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
|
|
#define BP_I2C_STAT_MASTER_PRESENT 31
|
|
#define BM_I2C_STAT_MASTER_PRESENT 0x80000000
|
|
#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0
|
|
#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1
|
|
#define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000)
|
|
#define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
|
|
#define BP_I2C_STAT_SLAVE_PRESENT 30
|
|
#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000
|
|
#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0
|
|
#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1
|
|
#define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000)
|
|
#define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
|
|
#define BP_I2C_STAT_ANY_ENABLED_IRQ 29
|
|
#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000
|
|
#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0
|
|
#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1
|
|
#define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000)
|
|
#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
|
|
#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16
|
|
#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000
|
|
#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000)
|
|
#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15
|
|
#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000
|
|
#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0
|
|
#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1
|
|
#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000)
|
|
#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
|
|
#define BP_I2C_STAT_SLAVE_FOUND 14
|
|
#define BM_I2C_STAT_SLAVE_FOUND 0x4000
|
|
#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0
|
|
#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1
|
|
#define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000)
|
|
#define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
|
|
#define BP_I2C_STAT_SLAVE_SEARCHING 13
|
|
#define BM_I2C_STAT_SLAVE_SEARCHING 0x2000
|
|
#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0
|
|
#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1
|
|
#define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000)
|
|
#define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
|
|
#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12
|
|
#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000
|
|
#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0
|
|
#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1
|
|
#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000)
|
|
#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
|
|
#define BP_I2C_STAT_BUS_BUSY 11
|
|
#define BM_I2C_STAT_BUS_BUSY 0x800
|
|
#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0
|
|
#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1
|
|
#define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800)
|
|
#define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
|
|
#define BP_I2C_STAT_CLK_GEN_BUSY 10
|
|
#define BM_I2C_STAT_CLK_GEN_BUSY 0x400
|
|
#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0
|
|
#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1
|
|
#define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400)
|
|
#define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
|
|
#define BP_I2C_STAT_DATA_ENGINE_BUSY 9
|
|
#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200
|
|
#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0
|
|
#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1
|
|
#define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200)
|
|
#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
|
|
#define BP_I2C_STAT_SLAVE_BUSY 8
|
|
#define BM_I2C_STAT_SLAVE_BUSY 0x100
|
|
#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0
|
|
#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1
|
|
#define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100)
|
|
#define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
|
|
#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7
|
|
#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80
|
|
#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80)
|
|
#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
|
|
#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6
|
|
#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40
|
|
#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40)
|
|
#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
|
|
#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5
|
|
#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20
|
|
#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20)
|
|
#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
|
|
#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4
|
|
#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10
|
|
#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10)
|
|
#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
|
|
#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3
|
|
#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8
|
|
#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8)
|
|
#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
|
|
#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2
|
|
#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4
|
|
#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4)
|
|
#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
|
|
#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1
|
|
#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2
|
|
#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2)
|
|
#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
|
|
#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0
|
|
#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1
|
|
#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0
|
|
#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1
|
|
#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1)
|
|
#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_I2C_DATA
|
|
* Address: 0x60
|
|
* SCT: no
|
|
*/
|
|
#define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
|
|
#define BP_I2C_DATA_DATA 0
|
|
#define BM_I2C_DATA_DATA 0xffffffff
|
|
#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
|
|
|
|
/**
|
|
* Register: HW_I2C_DEBUG0
|
|
* Address: 0x70
|
|
* SCT: yes
|
|
*/
|
|
#define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
|
|
#define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
|
|
#define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
|
|
#define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
|
|
#define BP_I2C_DEBUG0_DMAREQ 31
|
|
#define BM_I2C_DEBUG0_DMAREQ 0x80000000
|
|
#define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000)
|
|
#define BP_I2C_DEBUG0_DMAENDCMD 30
|
|
#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000
|
|
#define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000)
|
|
#define BP_I2C_DEBUG0_DMAKICK 29
|
|
#define BM_I2C_DEBUG0_DMAKICK 0x20000000
|
|
#define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000)
|
|
#define BP_I2C_DEBUG0_TBD 26
|
|
#define BM_I2C_DEBUG0_TBD 0x1c000000
|
|
#define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000)
|
|
#define BP_I2C_DEBUG0_DMA_STATE 16
|
|
#define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000
|
|
#define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000)
|
|
#define BP_I2C_DEBUG0_START_TOGGLE 15
|
|
#define BM_I2C_DEBUG0_START_TOGGLE 0x8000
|
|
#define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000)
|
|
#define BP_I2C_DEBUG0_STOP_TOGGLE 14
|
|
#define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000
|
|
#define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000)
|
|
#define BP_I2C_DEBUG0_GRAB_TOGGLE 13
|
|
#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000
|
|
#define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000)
|
|
#define BP_I2C_DEBUG0_CHANGE_TOGGLE 12
|
|
#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000
|
|
#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000)
|
|
#define BP_I2C_DEBUG0_TESTMODE 11
|
|
#define BM_I2C_DEBUG0_TESTMODE 0x800
|
|
#define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800)
|
|
#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10
|
|
#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400
|
|
#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
|
|
#define BP_I2C_DEBUG0_SLAVE_STATE 0
|
|
#define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff
|
|
#define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff)
|
|
|
|
/**
|
|
* Register: HW_I2C_DEBUG1
|
|
* Address: 0x80
|
|
* SCT: yes
|
|
*/
|
|
#define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
|
|
#define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
|
|
#define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
|
|
#define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
|
|
#define BP_I2C_DEBUG1_I2C_CLK_IN 31
|
|
#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000
|
|
#define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000)
|
|
#define BP_I2C_DEBUG1_I2C_DATA_IN 30
|
|
#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000
|
|
#define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000)
|
|
#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24
|
|
#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000
|
|
#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000)
|
|
#define BP_I2C_DEBUG1_CLK_GEN_STATE 16
|
|
#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000
|
|
#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000)
|
|
#define BP_I2C_DEBUG1_LST_MODE 9
|
|
#define BM_I2C_DEBUG1_LST_MODE 0x600
|
|
#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0
|
|
#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1
|
|
#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2
|
|
#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3
|
|
#define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600)
|
|
#define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
|
|
#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8
|
|
#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100
|
|
#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100)
|
|
#define BP_I2C_DEBUG1_FORCE_CLK_ON 5
|
|
#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20
|
|
#define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20)
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#define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4
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#define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10
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#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10)
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#define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3
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#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8
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#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8)
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#define BP_I2C_DEBUG1_FORCE_RCV_ACK 2
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#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4
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#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4)
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#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1
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#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2
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#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2)
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#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0
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#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1
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#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1)
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#endif /* __HEADERGEN__STMP3600__I2C__H__ */
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