161 lines
5.6 KiB
C
161 lines
5.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 Cástor Muñoz
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* Code based on openiBoot project
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __GPIO_S5L8702_H__
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#define __GPIO_S5L8702_H__
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#include <stdint.h>
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#define REG32_PTR_T volatile uint32_t *
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/*
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* s5l8702 External (GPIO) Interrupt Controller
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*
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* 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
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* to groups 6..3 in reverse order.
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* On group 3, last four bits are dissbled (GPIO 124..127).
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* All bits in groups 1 and 2 are disabled (not used).
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* On group 0, all bits are masked except bits 0 and 2:
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* bit 0: if unmasked, EINT6 is generated when ALVTCNT
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* reachs ALVTEND.
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* bit 2: if unmasked, EINT6 is generated when USB cable
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* is plugged and/or(TBC) unplugged.
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*
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* EIC_GROUP0..6 are connected to EINT6..0 of the VIC.
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*/
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#define EIC_N_GROUPS 7
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/* get EIC group and bit for a given GPIO port */
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#define EIC_GROUP(n) (6 - ((n) >> 5))
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#define EIC_INDEX(n) ((0x18 - ((n) & 0x18)) | ((n) & 0x7))
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/* SoC EINTs uses these 'gpio' numbers */
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#define GPIO_EINT_USB 0xd8
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#define GPIO_EINT_ALIVE 0xda
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/* probably a part of the system controller */
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#define EIC_BASE 0x39a00000
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#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
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#define EIC_INTSTAT(g) (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
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#define EIC_INTEN(g) (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
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#define EIC_INTTYPE(g) (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
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#define EIC_INTLEVEL_LOW 0
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#define EIC_INTLEVEL_HIGH 1
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#define EIC_INTTYPE_EDGE 0
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#define EIC_INTTYPE_LEVEL 1
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struct eint_handler {
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uint8_t gpio_n;
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uint8_t type; /* EIC_INTTYPE_ */
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uint8_t level; /* EIC_INTLEVEL_ */
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uint8_t autoflip;
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void (*isr)(struct eint_handler*);
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};
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void eint_init(void);
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void eint_register(struct eint_handler *h);
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void eint_unregister(struct eint_handler *h);
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void gpio_preinit(void);
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void gpio_init(void);
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/* get/set configuration for GPIO groups (0..15) */
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uint32_t gpio_group_get(int group);
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void gpio_group_set(int group, uint32_t mask, uint32_t cfg);
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/*
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* This is very preliminary work in progress, ATM this region is called
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* system 'alive' because it seems there are similiarities when mixing
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* concepts from:
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* - s3c2440 datasheet (figure 7-12, Sleep mode) and
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* - ARM-DDI-0287B (2.1.8 System Mode Control, Sleep an Doze modes)
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*
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* Known components:
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* - independent clocking
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* - 32-bit timer
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* - level/edge configurable interrupt controller
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*
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*
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* OSCSEL
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* |\ CKSEL
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* OSC0 -->| | |\
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* | |--->| | _________ ___________
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* OSC1 -->| | | | | | SClk | |
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* |/ | |--->| 1/CKDIV |---------->| 1/ALVTDIV |--> Timer
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* | | |_________| | |___________| counter
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* PClk --------->| | | ___________
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* |/ | | |
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* +-->| 1/UNKDIV |--> Unknown
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* |___________|
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*/
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#define SYSALV_BASE 0x39a00000
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#define ALVCON (*((REG32_PTR_T)(SYSALV_BASE + 0x0)))
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#define ALVUNK4 (*((REG32_PTR_T)(SYSALV_BASE + 0x4)))
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#define ALVUNK100 (*((REG32_PTR_T)(SYSALV_BASE + 0x100)))
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#define ALVUNK104 (*((REG32_PTR_T)(SYSALV_BASE + 0x104)))
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/*
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* System Alive control register
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*/
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#define ALVCON_CKSEL_BIT (1 << 25) /* 0 -> S5L8702_OSCx, 1 -> PClk */
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#define ALVCON_CKDIVEN_BIT (1 << 24) /* 0 -> CK divider Off, 1 -> On */
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#define ALVCON_CKDIV_POS 20 /* real_val = reg_val+1 */
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#define ALVCON_CKDIV_MSK 0xf
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/* UNKDIV: real_val = reg_val+1 (TBC), valid reg_val=0,1,2 */
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/* experimental: for registers in this region, read/write speed is
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* scaled by this divider, so probably it is related with internal
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* 'working' frequency.
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*/
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#define ALVCON_UNKDIV_POS 16
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#define ALVCON_UNKDIV_MSK 0x3
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/* bits[14:1] are UNKNOWN */
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#define ALVCON_OSCSEL_BIT (1 << 0) /* 0 -> OSC0, 1 -> OSC1 */
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/*
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* System Alive timer
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*
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* ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
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* is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
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* and ALVUNK4[0] are set, optionally an interrupt is generated (see
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* GPIO_EINT_ALIVE). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
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* and ALVUNK4[0], and initializes ALVTCNT to zero.
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*/
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#define ALVTCOM (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
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#define ALVTCOM_RUN_BIT (1 << 0) /* 0 -> Stop, 1 -> Start */
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#define ALVTCOM_RST_BIT (1 << 1) /* 1 -> Reset */
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#define ALVTEND (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
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#define ALVTDIV (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
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#define ALVTCNT (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
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#define ALVTSTAT (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
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#endif /* __GPIO_S5L8702_H__ */
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