312 lines
8.4 KiB
C
312 lines
8.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2009 Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <string.h>
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#include "config.h"
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#include "system.h"
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#include "audio.h"
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#include "s5l8700.h"
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#include "panic.h"
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#include "audiohw.h"
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#include "pcm.h"
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#include "pcm-internal.h"
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#include "pcm_sampr.h"
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#include "dma-target.h"
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#include "mmu-arm.h"
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/* Driver for the IIS/PCM part of the s5l8700 using DMA
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Notes:
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- pcm_play_dma_stop is untested, not sure if implemented the right way
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- recording is not implemented
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*/
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static volatile int locked = 0;
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static const int zerosample = 0;
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static unsigned char dblbuf[1024] IBSS_ATTR;
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static const void* queuedbuf;
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static size_t queuedsize;
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static const void* nextbuf;
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static size_t nextsize;
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static const struct div_entry {
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int pdiv, mdiv, sdiv, cdiv;
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} div_table[HW_NUM_FREQ] = {
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#ifdef IPOD_NANO2G
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[HW_FREQ_11] = { 0, 41, 3, 8},
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[HW_FREQ_22] = { 0, 41, 3, 4},
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[HW_FREQ_44] = { 0, 41, 3, 2},
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[HW_FREQ_88] = { 0, 41, 3, 1},
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[HW_FREQ_8 ] = { 0, 2, 1, 9},
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[HW_FREQ_16] = { 0, 2, 0, 9},
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[HW_FREQ_32] = { 2, 2, 0, 9},
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[HW_FREQ_64] = { 6, 2, 0, 9},
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[HW_FREQ_12] = { 0, 2, 2, 3},
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[HW_FREQ_24] = { 0, 2, 1, 3},
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[HW_FREQ_48] = { 0, 2, 0, 3},
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[HW_FREQ_96] = { 2, 2, 0, 3},
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#else
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/* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
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[HW_FREQ_11] = { 26, 189, 3, 8},
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[HW_FREQ_22] = { 50, 98, 2, 8},
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[HW_FREQ_44] = { 37, 151, 1, 9},
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[HW_FREQ_88] = { 50, 98, 1, 4},
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#if 0 /* disabled because the codec driver does not support it (yet) */
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[HW_FREQ_8 ] = { 28, 192, 3, 12},
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[HW_FREQ_16] = { 28, 192, 3, 6},
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[HW_FREQ_32] = { 28, 192, 2, 6},
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[HW_FREQ_12] = { 28, 192, 3, 8},
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[HW_FREQ_24] = { 28, 192, 2, 8},
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[HW_FREQ_48] = { 28, 192, 2, 4},
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[HW_FREQ_96] = { 28, 192, 1, 4},
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#endif
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#endif
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};
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/* Mask the DMA interrupt */
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void pcm_play_lock(void)
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{
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if (locked++ == 0) {
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INTMSK &= ~(1 << 10);
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}
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}
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/* Unmask the DMA interrupt if enabled */
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void pcm_play_unlock(void)
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{
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if (--locked == 0) {
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INTMSK |= (1 << 10);
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}
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}
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void INT_DMA(void) ICODE_ATTR;
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void INT_DMA(void)
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{
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bool new_buffer = false;
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DMACOM0 = 7;
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while (!(DMACON0 & (1 << 18)))
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{
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if (queuedsize)
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{
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memcpy(dblbuf, queuedbuf, queuedsize);
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DMABASE0 = (unsigned int)dblbuf;
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DMATCNT0 = queuedsize / 2 - 1;
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queuedsize = 0;
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}
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else
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{
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if (!nextsize)
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{
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new_buffer = pcm_play_dma_complete_callback(
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PCM_DMAST_OK, &nextbuf, &nextsize);
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if (!new_buffer)
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break;
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}
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queuedsize = MIN(sizeof(dblbuf), nextsize / 2);
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nextsize -= queuedsize;
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queuedbuf = nextbuf + nextsize;
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DMABASE0 = (unsigned int)nextbuf;
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DMATCNT0 = nextsize / 2 - 1;
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nextsize = 0;
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}
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commit_dcache();
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DMACOM0 = 4;
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DMACOM0 = 7;
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if (new_buffer)
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{
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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new_buffer = false;
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}
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}
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}
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void pcm_play_dma_start(const void* addr, size_t size)
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{
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/* DMA channel on */
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nextbuf = addr;
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nextsize = size;
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queuedsize = 0;
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DMABASE0 = (unsigned int)(&zerosample);
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DMATCNT0 = 0;
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DMACOM0 = 4;
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/* IIS Tx clock on */
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I2SCLKCON = (1 << 0); /* 1 = power on */
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/* IIS Tx on */
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I2STXCOM = (1 << 3) | /* 1 = transmit mode on */
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(1 << 2) | /* 1 = I2S interface enable */
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(1 << 1) | /* 1 = DMA request enable */
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(0 << 0); /* 0 = LRCK on */
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}
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void pcm_play_dma_stop(void)
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{
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/* DMA channel off */
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DMACOM0 = 5;
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/* IIS Tx off */
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I2STXCOM = (1 << 3) | /* 1 = transmit mode on */
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(0 << 2) | /* 1 = I2S interface enable */
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(1 << 1) | /* 1 = DMA request enable */
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(0 << 0); /* 0 = LRCK on */
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}
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static void pcm_dma_set_freq(enum hw_freq_indexes idx)
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{
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struct div_entry div = div_table[idx];
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/* configure PLL1 and MCLK for the desired sample rate */
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PLL1PMS = (div.pdiv << 16) |
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(div.mdiv << 8) |
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(div.sdiv << 0);
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PLL1LCNT = 280; /* 150 microseconds */
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/* enable PLL1 and wait for lock */
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PLLCON |= 1 << 1;
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while ((PLLLOCK & (1 << 1)) == 0);
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/* configure MCLK */
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CLKCON = (CLKCON & ~(0xFF)) |
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(0 << 7) | /* MCLK_MASK */
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(2 << 5) | /* MCLK_SEL = PLL1 */
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(1 << 4) | /* MCLK_DIV_ON */
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(div.cdiv - 1); /* MCLK_DIV_VAL */
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}
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void pcm_play_dma_init(void)
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{
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/* configure IIS pins */
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#ifdef IPOD_NANO2G
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PCON5 = (PCON5 & ~(0xFFFF0000)) | 0x77720000;
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PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
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#else
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PCON7 = (PCON7 & ~(0x0FFFFF00)) | 0x02222200;
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#endif
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/* configure DMA channel */
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DMACON0 = (0 << 30) | /* DEVSEL */
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(1 << 29) | /* DIR */
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(0 << 24) | /* SCHCNT */
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(1 << 22) | /* DSIZE */
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(0 << 19) | /* BLEN */
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(0 << 18) | /* RELOAD */
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(0 << 17) | /* HCOMINT */
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(1 << 16) | /* WCOMINT */
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(0 << 0); /* OFFSET */
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/* Enable the DMA IRQ */
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INTMSK |= (1 << 10);
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/* setup PLL */
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pcm_dma_set_freq(HW_FREQ_44);
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/* enable clock to the IIS module */
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PWRCON &= ~(1 << 6);
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/* configure IIS core */
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#ifdef IPOD_NANO2G
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I2STXCON = (1 << 20) | /* undocumented */
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(0 << 16) | /* burst length */
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(0 << 15) | /* 0 = falling edge */
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(0 << 13) | /* 0 = basic I2S format */
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(0 << 12) | /* 0 = MSB first */
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(0 << 11) | /* 0 = left channel for low polarity */
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(3 << 8) | /* MCLK divider */
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(0 << 5) | /* 0 = 16-bit */
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(2 << 3) | /* bit clock per frame */
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(1 << 0); /* channel index */
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#else
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I2STXCON = (DMA_IISOUT_BLEN << 16) | /* burst length */
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(0 << 15) | /* 0 = falling edge */
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(0 << 13) | /* 0 = basic I2S format */
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(0 << 12) | /* 0 = MSB first */
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(0 << 11) | /* 0 = left channel for low polarity */
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(3 << 8) | /* MCLK divider */
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(0 << 5) | /* 0 = 16-bit */
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(0 << 3) | /* bit clock per frame */
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(1 << 0); /* channel index */
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#endif
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audiohw_preinit();
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}
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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}
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/* set the configured PCM frequency */
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void pcm_dma_apply_settings(void)
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{
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pcm_dma_set_freq(pcm_fsel);
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}
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#ifdef HAVE_PCM_DMA_ADDRESS
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void * pcm_dma_addr(void *addr)
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{
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if (addr != NULL)
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addr = (void*)((uintptr_t)addr | 0x40000000);
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return addr;
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}
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#endif
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/****************************************************************************
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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void pcm_rec_lock(void)
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{
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}
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void pcm_rec_unlock(void)
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{
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}
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void pcm_rec_dma_stop(void)
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{
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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(void)addr;
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(void)size;
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}
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void pcm_rec_dma_close(void)
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{
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}
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void pcm_rec_dma_init(void)
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{
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}
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const void * pcm_rec_dma_get_peak_buffer(void)
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{
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return NULL;
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}
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#endif /* HAVE_RECORDING */
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