288 lines
6.2 KiB
C
288 lines
6.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "i2c-rk27xx.h"
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/* Driver for the rockchip rk27xx built-in I2C controller in master mode
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Both the i2c_read and i2c_write function take the following arguments:
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* slave, the address of the i2c slave device to read from / write to
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* address, optional sub-address in the i2c slave (unused if -1)
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* len, number of bytes to be transfered
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* data, pointer to data to be transfered
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A return value other than 0 indicates an error.
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*/
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static struct mutex i2c_mtx;
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static bool i2c_stop(void)
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{
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long timeout = current_tick + HZ/50;
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I2C_CONR |= (1<<4); /* NACK */
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I2C_LCMR |= (1<<2) | (1<<1); /* resume op, stop */
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while (I2C_LCMR & (1<<1))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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return true;
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}
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static bool i2c_write_byte(uint8_t data, bool start)
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{
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long timeout = current_tick + HZ/50;
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unsigned int isr_status;
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I2C_CONR = (1<<3) | (1<<2); /* master port enable, MTX mode, ACK enable */
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I2C_MTXR = data;
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if (start)
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I2C_LCMR = (1<<2) | (1<<0); /* resume op, start bit */
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else
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I2C_LCMR = (1<<2); /* resume op */
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/* wait for ACK from slave */
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do
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{
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isr_status = I2C_ISR;
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if (isr_status & (1<<7))
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{
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i2c_stop();
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I2C_ISR = 0;
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return false;
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}
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if (TIME_AFTER(current_tick, timeout))
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return false;
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} while ((isr_status & (1<<0)) == 0);
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/* clear status bit */
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I2C_ISR &= ~(1<<0);
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return true;
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}
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static bool i2c_read_byte(unsigned char *data)
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{
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long timeout = current_tick + HZ/50;
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I2C_LCMR = (1<<2); /* resume op */
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while (!(I2C_ISR & (1<<1)))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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*data = I2C_MRXR;
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/* clear status bit */
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I2C_ISR &= ~(1<<1);
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return true;
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}
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/* route i2c bus to internal codec or external bus
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* internal codec has 0x4e i2c slave address so
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* access to this address is routed to internal bus.
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* All other addresses are routed to external pads
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*/
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static void i2c_iomux(unsigned char slave)
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{
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unsigned long muxa = SCU_IOMUXA_CON & ~(0x1f<<14);
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if ((slave & 0xfe) == (0x27<<1))
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{
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/* internal codec */
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SCU_IOMUXA_CON = (muxa | (1<<16) | (1<<14));
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}
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else
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{
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/* external I2C bus */
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SCU_IOMUXA_CON = (muxa | (1<<18));
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}
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}
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void i2c_init(void)
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{
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mutex_init(&i2c_mtx);
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/* ungate i2c module clock */
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SCU_CLKCFG &= ~CLKCFG_I2C;
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I2C_OPR |= (1<<7); /* reset state machine */
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sleep(HZ/100);
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I2C_OPR &= ~((1<<7) | (1<<6)); /* clear ENABLE bit, deasert reset */
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/* set I2C divider to stay within allowed SCL freq limit
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* APBfreq = 50Mhz
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* I2C_div = (I2CCDVR[5:3] + 1) * 2^((I2CCDVR[2:0] + 1))
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* SCLfreq = APBfreq/(5*I2C_div)
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*
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* (5<<3) | (1<<0) 416.7 KHz (above spec)
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* (6<<3) | (1<<0) 357.1 kHz
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* (7<<3) | (1<<0) 312.4 kHz
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* (6<<3) | (2<<0) 178.6 kHz
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* (7<<3) | (2<<0) 156.3 kHz
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*/
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I2C_OPR = (I2C_OPR & ~(0x3F)) | (6<<3) | (1<<0);
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I2C_IER = 0x00;
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I2C_OPR |= (1<<6); /* enable i2c core */
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/* turn off i2c module clock until we need to comunicate */
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SCU_CLKCFG |= CLKCFG_I2C;
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}
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int i2c_write(unsigned char slave, int address, int len,
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const unsigned char *data)
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{
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int ret = 0;
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mutex_lock(&i2c_mtx);
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i2c_iomux(slave);
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/* ungate i2c clock */
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SCU_CLKCFG &= ~CLKCFG_I2C;
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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ret = 1;
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goto end;
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}
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if (address >= 0)
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{
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if (! i2c_write_byte(address, false))
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{
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ret = 2;
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goto end;
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}
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}
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/* write data */
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while (len--)
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{
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if (! i2c_write_byte(*data++, false))
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{
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ret = 4;
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goto end;
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}
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}
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/* STOP */
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if (! i2c_stop())
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{
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ret = 5;
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goto end;
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}
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end:
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mutex_unlock(&i2c_mtx);
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SCU_CLKCFG |= CLKCFG_I2C;
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return ret;
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}
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int i2c_read(unsigned char slave, int address, int len, unsigned char *data)
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{
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int ret = 0;
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mutex_lock(&i2c_mtx);
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i2c_iomux(slave);
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/* ungate i2c module clock */
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SCU_CLKCFG &= ~CLKCFG_I2C;
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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if (address >= 0)
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{
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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ret = 1;
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goto end;
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}
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/* write address */
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if (! i2c_write_byte(address, false))
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{
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ret = 2;
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goto end;
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}
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}
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/* (repeated) START */
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if (! i2c_write_byte(slave | 1, true))
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{
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ret = 3;
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goto end;
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}
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I2C_CONR = (1<<2); /* master port enable, MRX mode, ACK enable */
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while (len)
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{
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if (! i2c_read_byte(data++))
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{
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ret = 4;
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goto end;
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}
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if (len == 1)
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I2C_CONR |= (1<<4); /* NACK */
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else
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I2C_CONR &= ~(1<<4); /* ACK */
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len--;
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}
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/* STOP */
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if (! i2c_stop())
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{
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ret = 5;
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goto end;
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}
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end:
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mutex_unlock(&i2c_mtx);
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SCU_CLKCFG |= CLKCFG_I2C;
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return ret;
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}
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