04fe77a465
It was barely even a stub, and hasn't seen any development since 2009 Change-Id: I0aa15d9a7b90ae8c771924d9f401380d4cc0fab9
668 lines
21 KiB
C
668 lines
21 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "thread.h"
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#include "i2s.h"
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#include "i2c-pp.h"
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#include "as3514.h"
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#ifdef HAVE_HOTSWAP
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#include "sd-pp-target.h"
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#endif
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#include "button-target.h"
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#include "usb_drv.h"
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/* Bit 0 - 20: Cached Address */
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#define CACHE_ADDRESS_MASK ((1<<21)-1)
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/* Bit 22: Cache line dirty */
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#define CACHE_LINE_DIRTY (1<<22)
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/* Bit 23: Cache line valid */
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#define CACHE_LINE_VALID (1<<23)
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/* Cache Size - 8K*/
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#define CACHE_SIZE 0x2000
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/*Initial memory address used to prime cache
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* could be targeted to a more 'important' address
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* Note: Don't start at 0x0, as the compiler thinks it's a
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* null pointer dereference and will helpfully blow up the code. */
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#define CACHED_INIT_ADDR CACHEALIGN_UP(0x2000)
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#if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE)
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extern void TIMER1(void);
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extern void TIMER2(void);
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extern void SERIAL_ISR(void);
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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static struct corelock cpufreq_cl SHAREDBSS_ATTR;
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#endif
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#if defined(IPOD_VIDEO) && !defined(BOOTLOADER)
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unsigned char probed_ramsize;
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#endif
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void __attribute__((interrupt("IRQ"))) irq_handler(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK) {
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TIMER1();
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}
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else if (CPU_INT_STAT & TIMER2_MASK) {
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TIMER2();
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}
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#ifdef HAVE_USBSTACK
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/* Rather high priority - place near front */
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else if (CPU_INT_STAT & USB_MASK) {
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usb_drv_int();
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}
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#endif
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#if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if ((GPIOA_INT_STAT & 0x3f) || (GPIOB_INT_STAT & 0x30))
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ipod_mini_button_int();
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if (GPIOC_INT_STAT & 0x02)
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firewire_insert_int();
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if (GPIOD_INT_STAT & 0x08)
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usb_insert_int();
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}
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/* end IPOD_MINI */
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#elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
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else if (CPU_HI_INT_STAT & I2C_MASK) {
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ipod_4g_button_int();
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}
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#if defined(IPOD_COLOR) || defined(IPOD_MINI2G) || defined(IPOD_4G)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOC_INT_STAT & 0x02)
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firewire_insert_int();
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if (GPIOD_INT_STAT & 0x08)
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usb_insert_int();
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}
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#elif defined(IPOD_NANO) || defined(IPOD_VIDEO)
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x10)
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usb_insert_int();
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}
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#endif
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/* end CONFIG_KEYPAD == IPOD_4G_PAD */
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#elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x04)
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usb_insert_int();
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}
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/* end IRIVER_H10 || IRIVER_H10_5GB */
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#elif defined(SANSA_E200)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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#ifdef HAVE_HOTSWAP
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if (GPIOA_INT_STAT & 0x80)
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microsd_int();
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#endif
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if (GPIOB_INT_STAT & 0x10)
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usb_insert_int();
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}
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else if (CPU_HI_INT_STAT & GPIO1_MASK) {
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if (GPIOF_INT_STAT & 0xff)
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button_int();
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if (GPIOH_INT_STAT & 0xc0)
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clickwheel_int();
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}
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/* end SANSA_E200 */
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#elif defined(SANSA_C200)
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else if (CPU_HI_INT_STAT & GPIO1_MASK) {
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if (GPIOH_INT_STAT & 0x02)
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usb_insert_int();
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}
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#ifdef HAVE_HOTSWAP
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x08)
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microsd_int();
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}
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#endif
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/* end SANSA_C200 */
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#elif defined(MROBE_100)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOD_INT_STAT & 0x02)
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button_int();
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if (GPIOD_INT_STAT & 0x80)
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headphones_int();
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}
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x04)
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usb_insert_int();
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}
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/* end MROBE_100 */
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#elif defined(PHILIPS_SA9200)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOD_INT_STAT & 0x02)
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button_int();
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if (GPIOB_INT_STAT & 0x40)
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usb_insert_int();
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}
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/* end PHILIPS_SA9200 */
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#elif defined(PHILIPS_HDD1630) || defined(PHILIPS_HDD6330)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOA_INT_STAT & 0x20)
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button_int();
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}
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else if (CPU_HI_INT_STAT & GPIO1_MASK) {
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if (GPIOE_INT_STAT & 0x04)
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usb_insert_int();
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}
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/* end PHILIPS_HDD1630 || PHILIPS_HDD6330 */
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#elif defined(SAMSUNG_YH820) || defined(SAMSUNG_YH920) || defined(SAMSUNG_YH925)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOD_INT_STAT & 0x10)
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usb_insert_int();
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#if !defined(SAMSUNG_YH820)
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if (GPIOD_INT_STAT & 0x01)
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remote_int();
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#endif
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}
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/* end SAMSUNG_YHxxx */
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#elif defined(PBELL_VIBE500)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOA_INT_STAT & 0x20)
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button_int();
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}
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x04)
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usb_insert_int();
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}
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/* end PBELL_VIBE500 */
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#endif
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#ifdef IPOD_ACCESSORY_PROTOCOL
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else if (CPU_HI_INT_STAT & (SER0_MASK | SER1_MASK)) {
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SERIAL_ISR();
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}
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#endif
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} else {
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if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif /* BOOTLOADER || HAVE_BOOTLOADER_USB_MODE */
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#if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE)
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static void disable_all_interrupts(void)
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{
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COP_HI_INT_DIS = -1;
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CPU_HI_INT_DIS = -1;
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HI_INT_FORCED_CLR = -1;
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COP_INT_DIS = -1;
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CPU_INT_DIS = -1;
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INT_FORCED_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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GPIOE_INT_EN = 0;
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GPIOF_INT_EN = 0;
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GPIOG_INT_EN = 0;
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GPIOH_INT_EN = 0;
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GPIOI_INT_EN = 0;
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GPIOJ_INT_EN = 0;
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GPIOK_INT_EN = 0;
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GPIOL_INT_EN = 0;
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}
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void ICODE_ATTR commit_dcache(void)
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{
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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CACHE_OPERATION |= CACHE_OP_FLUSH;
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while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
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nop; nop; nop; nop;
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}
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}
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static void ICODE_ATTR cache_invalidate_special(void)
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{
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/* Cache lines which are not marked as valid can cause memory
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* corruption when there are many writes to and code fetches from
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* cached memory. This workaround points all cache status to the
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* maximum line address and marked valid but not dirty. Since that area
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* is never accessed, the cache lines don't affect anything, and
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* they're effectively discarded. Interrupts must be disabled here
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* because any change they make to cached memory could be discarded.
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* A status word is 32 bits and is mirrored four times for each cache line
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bit 0-20 line_address >> 11
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bit 21 unused?
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bit 22 line_dirty
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bit 23 line_valid
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bit 24-31 unused?
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*/
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register volatile unsigned long *p;
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if (CURRENT_CORE == CPU)
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{
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for (p = &CACHE_STATUS_BASE_CPU;
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p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE/sizeof(*p);
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p += CACHEALIGN_SIZE/sizeof(*p))
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*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
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}
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else
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{
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for (p = &CACHE_STATUS_BASE_COP;
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p < (&CACHE_STATUS_BASE_COP) + CACHE_SIZE/sizeof(*p);
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p += CACHEALIGN_SIZE/sizeof(*p))
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*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
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}
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}
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void ICODE_ATTR commit_discard_idcache(void)
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{
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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register int istat = disable_interrupt_save(IRQ_FIQ_STATUS);
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commit_dcache();
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cache_invalidate_special();
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restore_interrupt(istat);
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}
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}
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void commit_discard_dcache(void) __attribute__((alias("commit_discard_idcache")));
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static void init_cache(void)
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{
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/* Initialising the cache in the iPod bootloader may prevent Rockbox from starting
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* depending on the model */
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/* cache init mode */
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CACHE_CTL &= ~(CACHE_CTL_ENABLE | CACHE_CTL_RUN);
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CACHE_CTL |= CACHE_CTL_INIT;
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#ifndef BOOTLOADER
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/* what's this do? */
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CACHE_PRIORITY |= (CURRENT_CORE == CPU) ? 0x10 : 0x20;
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#endif
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/* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
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* yes: 0x00000000 - 0x03ffffff
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* no: 0x04000000 - 0x1fffffff
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* yes: 0x20000000 - 0x23ffffff
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* no: 0x24000000 - 0x3fffffff
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*/
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CACHE_MASK = 0x00001c00;
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CACHE_OPERATION = 0xfc0;
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/* enable cache */
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CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
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nop; nop; nop; nop;
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/* Ensure all cache lines are valid for the next flush. Since this
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* can run from cached RAM, rewriting of cache status words may not
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* be safe and the cache is filled instead by reading. */
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register volatile char *p = (volatile char *)CACHED_INIT_ADDR;
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for (;p < (volatile char *)CACHED_INIT_ADDR + CACHE_SIZE; p += CACHEALIGN_SIZE)
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(void)*p;
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}
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#endif /* BOOTLOADER || HAVE_BOOTLOADER_USB_MODE */
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/* We need this for Sansas since we boost the cpu in their bootloader */
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#if !defined(BOOTLOADER) || (defined(SANSA_E200) || defined(SANSA_C200) || \
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defined(PHILIPS_SA9200))
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void scale_suspend_core(bool suspend) ICODE_ATTR;
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void scale_suspend_core(bool suspend)
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{
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unsigned int core = CURRENT_CORE;
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IF_COP( unsigned int othercore = 1 - core; )
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static int oldstatus IBSS_ATTR;
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if (suspend)
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{
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oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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IF_COP( PROC_CTL(othercore) = 0x40000000; nop; )
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PROC_CTL(core) = 0x48000003; nop;
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}
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else
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{
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PROC_CTL(core) = 0x4800001f; nop;
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IF_COP( PROC_CTL(othercore) = 0x00000000; nop; )
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restore_interrupt(oldstatus);
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}
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#if NUM_CORES > 1
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void set_cpu_frequency__lock(void)
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{
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corelock_lock(&cpufreq_cl);
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}
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void set_cpu_frequency__unlock(void)
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{
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corelock_unlock(&cpufreq_cl);
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}
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#endif /* NUM_CORES > 1 */
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void set_cpu_frequency(long frequency) ICODE_ATTR;
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void set_cpu_frequency(long frequency)
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#else
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static void pp_set_cpu_frequency(long frequency)
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#endif
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{
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switch (frequency)
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{
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/* Note1: The PP5022 PLL must be run at >= 96MHz
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* Bits 20..21 select the post divider (1/2/4/8).
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* PP5026 is similar to PP5022 except it doesn't
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* have this limitation (and the post divider?)
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* Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
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* 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
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* SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
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* FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */
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case CPUFREQ_SLEEP:
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cpu_frequency = CPUFREQ_SLEEP;
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PLL_CONTROL |= 0x0c000000;
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
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scale_suspend_core(false);
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
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break;
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case CPUFREQ_MAX:
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cpu_frequency = CPUFREQ_MAX;
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DEV_INIT2 |= INIT_PLL; /* enable PLL power */
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PLL_CONTROL |= 0x88000000; /* enable PLL */
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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scale_suspend_core(false);
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG |= 0x10000000; /* set ">65MHz" bit */
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#endif
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
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PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */
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PLL_CONTROL = 0x8a020a03; /* repeat setup */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a121403; /* 80 MHz = (20/3 * 24MHz) / 2 */
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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scale_suspend_core(true);
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DEV_TIMING1 = 0x00000808;
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CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
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scale_suspend_core(false);
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break;
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#if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/
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case CPUFREQ_NORMAL:
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cpu_frequency = CPUFREQ_NORMAL;
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PLL_CONTROL |= 0x08000000;
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
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#endif
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scale_suspend_core(false);
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
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break;
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#else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
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case CPUFREQ_NORMAL:
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cpu_frequency = CPUFREQ_NORMAL;
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DEV_INIT2 |= INIT_PLL; /* enable PLL power */
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PLL_CONTROL |= 0x88000000; /* enable PLL */
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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scale_suspend_core(false);
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
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#endif
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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scale_suspend_core(true);
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DEV_TIMING1 = 0x00000303;
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CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
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scale_suspend_core(false);
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break;
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#endif /******** CPUFREQ_NORMAL end ********/
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default:
|
|
cpu_frequency = CPUFREQ_DEFAULT;
|
|
PLL_CONTROL |= 0x08000000;
|
|
scale_suspend_core(true);
|
|
CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
|
|
DEV_TIMING1 = 0x00000303;
|
|
#if defined(IPOD_MINI2G)
|
|
MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
|
|
#elif defined(IPOD_NANO)
|
|
IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
|
|
#endif
|
|
scale_suspend_core(false);
|
|
PLL_CONTROL &= ~0x80000000; /* disable PLL */
|
|
DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
|
|
break;
|
|
}
|
|
}
|
|
#endif /* !BOOTLOADER || (SANSA_E200 || SANSA_C200 || PHILIPS_SA9200) */
|
|
|
|
#ifndef BOOTLOADER
|
|
void system_init(void)
|
|
{
|
|
if (CURRENT_CORE == CPU)
|
|
{
|
|
#if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
|
|
/* set minimum startup configuration */
|
|
DEV_EN = 0xc2000124;
|
|
DEV_EN2 = 0x00002000;
|
|
CACHE_PRIORITY = 0x0000003f;
|
|
GPO32_VAL = 0x20000000;
|
|
DEV_INIT1 = 0xdc000000;
|
|
DEV_INIT2 = 0x40000000;
|
|
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3dfffef8;
|
|
DEV_RS2 = 0xffffdfff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined (IPOD_VIDEO)
|
|
/* set minimum startup configuration */
|
|
DEV_EN = 0xc2000124;
|
|
DEV_EN2 = 0x00000000;
|
|
CACHE_PRIORITY = 0x0000003f;
|
|
GPO32_VAL &= 0x00004000;
|
|
DEV_INIT1 = 0x00000000;
|
|
DEV_INIT2 = 0x40000000;
|
|
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3dfffef8;
|
|
DEV_RS2 = 0xffffffff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined (IPOD_NANO)
|
|
/* set minimum startup configuration */
|
|
DEV_EN = 0xc2000124;
|
|
DEV_EN2 = 0x00002000;
|
|
CACHE_PRIORITY = 0x0000003f;
|
|
GPO32_VAL = 0x50000000;
|
|
DEV_INIT1 = 0xa8000000;
|
|
DEV_INIT2 = 0x40000000;
|
|
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3ffffef8;
|
|
DEV_RS2 = 0xffffdfff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined(SANSA_C200) || defined (SANSA_E200)
|
|
/* set minimum startup configuration */
|
|
DEV_EN = 0xc4000124;
|
|
DEV_EN2 = 0x00000000;
|
|
CACHE_PRIORITY = 0x0000003f;
|
|
GPO32_VAL = 0x10000000;
|
|
DEV_INIT1 = 0x54000000;
|
|
DEV_INIT2 = 0x40000000;
|
|
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3bfffef8;
|
|
DEV_RS2 = 0xffffffff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined(PHILIPS_SA9200)
|
|
DEV_INIT1 = 0x00000000;
|
|
DEV_INIT2 = 0x40004000;
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3ffffef8;
|
|
DEV_RS2 = 0xffffffff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined(IPOD_4G)
|
|
/* set minimum startup configuration */
|
|
DEV_EN = 0xc2020124;
|
|
DEV_EN2 = 0x00000000;
|
|
CACHE_PRIORITY = 0x0000003f;
|
|
GPO32_VAL = 0x02000000;
|
|
DEV_INIT1 = 0x00000000;
|
|
DEV_INIT2 = 0x40000000;
|
|
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3dfdfef8;
|
|
DEV_RS2 = 0xffffffff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#elif defined (IPOD_MINI)
|
|
/* to be done */
|
|
#elif defined (IPOD_MINI2G)
|
|
/* to be done */
|
|
#elif defined (MROBE_100)
|
|
/* to be done */
|
|
#elif defined(PBELL_VIBE500)
|
|
/* reset all allowed devices */
|
|
DEV_RS = 0x3ffffef8;
|
|
DEV_RS2 = 0xffffffff;
|
|
DEV_RS = 0x00000000;
|
|
DEV_RS2 = 0x00000000;
|
|
#endif
|
|
|
|
#if !defined(SANSA_E200) && !defined(SANSA_C200) && !defined(PHILIPS_SA9200)
|
|
/* Remap the flash ROM on CPU, keep hidden from COP:
|
|
* 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
|
|
MMAP1_LOGICAL = 0x20003c00;
|
|
MMAP1_PHYSICAL = 0x00003084 |
|
|
MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
|
|
MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
|
|
#endif
|
|
|
|
disable_all_interrupts();
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
|
#if NUM_CORES > 1
|
|
corelock_init(&cpufreq_cl);
|
|
#endif
|
|
#else
|
|
pp_set_cpu_frequency(CPUFREQ_MAX);
|
|
#endif
|
|
|
|
#if defined(IPOD_VIDEO)
|
|
/* crt0-pp.S wrote the ram size to the last byte of the first 32MB
|
|
ram bank. See the comment there for how we determine it. */
|
|
volatile unsigned char *end32 = (volatile unsigned char *)0x01ffffff;
|
|
probed_ramsize = *end32;
|
|
#endif
|
|
}
|
|
|
|
init_cache();
|
|
}
|
|
|
|
#else /* BOOTLOADER */
|
|
|
|
void system_init(void)
|
|
{
|
|
/* Only the CPU gets here in the bootloader */
|
|
#ifdef HAVE_BOOTLOADER_USB_MODE
|
|
disable_all_interrupts();
|
|
init_cache();
|
|
/* Use the local vector map */
|
|
CACHE_CTL |= CACHE_CTL_VECT_REMAP;
|
|
#endif /* HAVE_BOOTLOADER_USB_MODE */
|
|
|
|
#if defined(SANSA_C200) || defined(SANSA_E200) || defined(PHILIPS_SA9200)
|
|
pp_set_cpu_frequency(CPUFREQ_MAX);
|
|
#endif
|
|
/* Else the frequency should get changed upon USB connect -
|
|
* decide per-target */
|
|
}
|
|
|
|
#ifdef HAVE_BOOTLOADER_USB_MODE
|
|
void system_prepare_fw_start(void)
|
|
{
|
|
disable_interrupt(IRQ_FIQ_STATUS);
|
|
tick_stop();
|
|
disable_all_interrupts();
|
|
/* Some OF's disable this themselves, others do not and will hang. */
|
|
CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
|
|
}
|
|
#endif /* HAVE_BOOTLOADER_USB_MODE */
|
|
#endif /* !BOOTLOADER */
|
|
|
|
void ICODE_ATTR system_reboot(void)
|
|
{
|
|
disable_interrupt(IRQ_FIQ_STATUS);
|
|
CPU_INT_DIS = -1;
|
|
COP_INT_DIS = -1;
|
|
|
|
/* Reboot */
|
|
#if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
|
|
CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
|
|
|
|
/* Magic used by the c200 OF: 0x23066000
|
|
Magic used by the c200 BL: 0x23066b7b
|
|
In both cases, the OF executes these 2 commands from iram. */
|
|
STRAP_OPT_A = 0x23066b7b;
|
|
DEV_RS = DEV_SYSTEM;
|
|
#else
|
|
DEV_RS |= DEV_SYSTEM;
|
|
#endif
|
|
/* wait until reboot kicks in */
|
|
while (1);
|
|
}
|
|
|
|
void system_exception_wait(void)
|
|
{
|
|
/* FIXME: we just need the right buttons */
|
|
CPU_INT_DIS = -1;
|
|
COP_INT_DIS = -1;
|
|
|
|
/* Halt */
|
|
PROC_CTL(CURRENT_CORE) = 0x40000000;
|
|
while (1);
|
|
}
|
|
|
|
int system_memory_guard(int newmode)
|
|
{
|
|
(void)newmode;
|
|
return 0;
|
|
}
|