f33330c0ff
Remove the implementations of all exceptions handlers from the various crt0.S files and have a single implementation in system-arm.h The new implementation is weak so that it can be overwritten by some specific code (like the unwinder) Change-Id: Ib3e041ed6037376bbe0e79286057e1051640dd90 Reviewed-on: http://gerrit.rockbox.org/205 Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
339 lines
10 KiB
ArmAsm
339 lines
10 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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.global start
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start:
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/* Exception vectors */
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b newstart
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b undef_instr_handler
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b software_int_handler
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b prefetch_abort_handler
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b data_abort_handler
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b reserved_handler
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/* These vectors are unused */
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subs pc, lr, #4 @ b irq_handler
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subs pc, lr, #4 @ b fiq_handler
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.balign 0x40, 0x6B
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/* Arm bootloader and startup code based on startup.s from the iPodLinux loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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*/
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/* Bootloader:
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* Initially this code is running at VA 0x8a000000 (PA 0x82000000).
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* The mapping stub is copied to IRAM (0x1fffc000), sets up the MMU and
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* jumps into the final VA remapping starting at 0x02000000 (32MB).
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*
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* Firmware:
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* This code will be running from VA 0x00000000 (PA 0x80000000) and perform
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* similar steps to the bootloader code.
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*/
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newstart:
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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adr r2, remap_start /* Load PC-relative labels (relocatable) */
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adr r3, remap_end
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ldr r5, =TTB_BASE_ADDR /* TTB pointer */
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ldr r6, =IRAM_BASE_ADDR
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mov r1, r6
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1: /* Copy remapping stub to IRAM */
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cmp r3, r2
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ldrhi r4, [r2], #4
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strhi r4, [r1], #4
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bhi 1b
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bx r6
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/* Remapping stub. No absolute addresses may be used until after the
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* remapping is complete. */
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remap_start:
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mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */
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tst r3, #(1 << 2) /* dcache? */
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tsteq r3, #(1 << 12) /* or icache? */
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mov r0, #0
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mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */
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mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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mcr p15, 0, r0, c13, c0, 0
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mcr p15, 0, r0, c13, c0, 1
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/* Also setup the Peripheral Port Remap register inside the core */
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mov r0, #0x40000000 /* start from AIPS 2GB region */
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add r0, r0, #0x15
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mcr p15, 0, r0, c15, c2, 4
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/*** L2 Cache setup/invalidation/disable ***/
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/* Disable L2 cache first */
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mov r0, #L2CC_BASE_ADDR
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mov r1, #0
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str r1, [r0, #L2_CACHE_CTL_REG]
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/* Disble L1 caches and memory manager */
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bic r3, r3, #(1 << 12) /* L1 I-cache disabled */
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bic r3, r3, #((1 << 2) | /* L1 D-cache disabled */ \
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(1 << 0)) /* MMU disabled */
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mcr p15, 0, r3, c1, c0, 0
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/*
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* Configure L2 Cache:
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* - 128k size(16k way)
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* - 8-way associativity
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* - 0 ws TAG/VALID/DIRTY
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* - 4 ws DATA R/W
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*/
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mov r1, #0x00130000
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orr r1, r1, #0x24
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str r1, [r0, #L2_CACHE_AUX_CTL_REG]
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/* Invalidate L2 */
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mov r1, #0x000000FF
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str r1, [r0, #L2_CACHE_INV_WAY_REG]
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1:
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/* Poll Invalidate By Way register */
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ldr r1, [r0, #L2_CACHE_INV_WAY_REG]
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cmp r1, #0
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bne 1b
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/*** End of L2 operations ***/
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/* TTB Initialisation */
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/* Set TTB base address */
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mcr p15, 0, r5, c2, c0, 0
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/* Set all domains to manager status */
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mvn r0, #0
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mcr p15, 0, r0, c3, c0, 0
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/* Set page tables */
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/* Map each memory loc to itself
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* not cached, not buffered */
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/* Physical address = 0x0 */
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mov r1, #(1 << 10) /* superuser - r/w, user - no access */
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orr r1, r1, #((0 << 5) | /* domain 0th */ \
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(1 << 4) | /* should be "1" */ \
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(1 << 1)) /* Section signature */
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mov r2, r5
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add r3, r5, #TTB_SIZE /* End position */
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1:
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str r1, [r2], #4
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add r1, r1, #(1 << 20) /* Next MB */
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cmp r2, r3
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blo 1b
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/* Bits 31:20 of r1 will be 0 due to wraparound in previous loop */
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/* Map PA:0x80000000-0x83ffffff to VA:0x00000000-0x03f00000
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* cached, buffered */
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mov r2, r5 /* TTB pointer */
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add r3, r5, #64*4 /* End position */
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orr r1, r1, #(0x80000000 | /* Physical address */ \
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(1 << 3) | /* cache flag */ \
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(1 << 2)) /* buffer flag */
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1:
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str r1, [r2], #4
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add r1, r1, #(1 << 20)
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cmp r2, r3
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blo 1b
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/* Map TTB, FRAME and QHARRAY section PA:0x83f00000-0x83ffffff to
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* VA:0x04000000-0x040fffff
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* not cache, buffered */
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sub r1, r1, #0x00100000
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bic r1, r1, #(1 << 3) /* clear cache flag */
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str r1, [r5, #64*4]
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/* Enable MMU */
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */
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/* Auxilliary control register */
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mrc p15, 0, r0, c1, c0, 1
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bic r0, r0, #((1 << 6) | /* Restrict cache size OFF */ \
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(1 << 5) | /* Enable block tranfer cache operations */ \
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(1 << 4) | /* Clean+Invalidate cache operation ON */ \
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(1 << 3)) /* Round-robin micro TLB replacement */
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orr r0, r0, #((1 << 2) | /* Static branch prediction ON */ \
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(1 << 1) | /* Dynamic branch prediction ON */ \
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(1 << 0)) /* Return stack enabled */
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mcr p15, 0, r0, c1, c0, 1
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/* Control register */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #((1 << 29) | /* AF by AP disabled */ \
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(1 << 28) | /* TEX remap disabled */ \
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(1 << 23)) /* Sub AP bits enabled (compatible) */
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bic r0, r0, #((1 << 21) | /* All performance features enabled */ \
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(1 << 15)) /* Loads to PC set T bit */
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bic r0, r0, #((1 << 13)) /* Low vectors */
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bic r0, r0, #((1 << 1)) /* Strict alignment disabled */
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orr r0, r0, #((1 << 24) | /* Vectored interrupt ON */ \
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(1 << 22)) /* Unaligned access support enabled */
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orr r0, r0, #((1 << 14) | /* Round-robin replacement for I/D caches */ \
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(1 << 12) | /* L1 I-cache enabled */ \
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(1 << 11) | /* Program flow prediction enabled */ \
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(1 << 9) | /* ROM protection enabled */ \
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(1 << 8)) /* MMU protection enabled */
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orr r0, r0, #((1 << 2) | /* L1 D-cache enabled */ \
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(1 << 0)) /* MMU enabled */
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldr pc, L_post_remap
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L_post_remap:
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.word remap_end
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remap_end:
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#ifdef BOOTLOADER
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/* Copy bootloader exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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#endif /* BOOTLOADER */
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#ifdef HAVE_INIT_ATTR
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/* copy init data to codec buffer */
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/* must be done before bss is zeroed */
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ldr r4, =_initcopy
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ldr r3, =_initend
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ldr r2, =_initstart
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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#endif /* HAVE_INIT_ATTR */
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/* Initialise bss and ncbss sections to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =irq_stack
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/* FIQ mode is unused, thus sp_FIQ is irrelevant for it */
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/* Set up stack for SVC mode */
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msr cpsr_c, #0xd3
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ldr sp, =svc_stack
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/* Let abort and undefined modes use irq stack */
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msr cpsr_c, #0xd7
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb
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ldr sp, =irq_stack
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r2, =stackbegin
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ldr r3, =0xdeadbeef
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1:
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cmp sp, r2
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strhi r3, [r2], #4
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bhi 1b
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#ifndef BOOTLOADER
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/* Enable access to VFP */
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mrc p15, 0, r3, c1, c0, 2
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orr r3, r3, #0xf00000
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mcr p15, 0, r3, c1, c0, 2
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/* Enable VFP */
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mrc p10, 7, r3, c8, c0, 0
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orr r3, r3, #1<<30
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mcr p10, 7, r3, c8, c0, 0
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/* Disable exceptions, enable default NaN, flush-to-zero, round toward 0 */
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mrc p10, 7, r3, c1, c0, 0
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orr r3, r3, #15<<22
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bic r3, r3, #31<<8
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mcr p10, 7, r3, c1, c0, 0
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#endif
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/* Make memory coherent for devices */
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bl commit_discard_idcache
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bl main
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#ifdef BOOTLOADER
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/* Exception vectors with absolute jumps for bootloader */
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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subs pc, lr, #4 @ ldr pc, [pc, #24]
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subs pc, lr, #4 @ ldr pc, [pc, #24]
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.word newstart
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.word undef_instr_handler
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.word software_int_handler
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.word prefetch_abort_handler
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.word data_abort_handler
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.word reserved_handler
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.word 0 @ irq_handler
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.word 0 @ fiq_handler
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#endif /* BOOTLOADER */
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/* 256 words of IRQ stack */
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.section .bss
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.balign 32
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.space 256*4
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irq_stack:
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/* 256 words of SVC stack */
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.section .bss
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.balign 32
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.space 256*4
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svc_stack:
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