618 lines
21 KiB
C
618 lines
21 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "system.h"
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#include "kernel.h"
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#include "action.h"
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#include "lcd.h"
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#include "font.h"
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#include "cpu.h"
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#include "pl180.h"
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#include "ascodec.h"
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#include "adc.h"
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#include "storage.h"
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#define DEBUG_CANCEL ACTION_STD_CANCEL
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#define DEBUG_NEXT ACTION_STD_NEXT
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#define DEBUG_LEFT_JUSTIFY ACTION_STD_OK
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#define DEBUG_LEFT_SCROLL ACTION_STD_MENU
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/* if the possiblity exists to divide by zero protect with this macro */
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#define DIV_FINITE(dividend, divisor) ((divisor == 0)? divisor : dividend/divisor)
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#define ON "Enabled"
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#define OFF "Disabled"
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#define CP15_MMU (1<<0) /* mmu off/on */
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#define CP15_DC (1<<2) /* dcache off/on */
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#define CP15_IC (1<<12) /* icache off/on */
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#define CLK_MAIN 24000000 /* 24 MHz */
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#define D_MHZ 1000000
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#define D_KHZ 1000
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enum dbg_clocks
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{
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CLK_PLLA = 0x0,
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CLK_PLLB,
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CLK_PROC,
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CLK_FCLK,
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CLK_EXTMEM,
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CLK_PCLK,
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CLK_IDE,
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CLK_I2C,
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CLK_I2SI,
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CLK_I2SO,
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CLK_DBOP,
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CLK_SD_MCLK_NAND,
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CLK_SD_MCLK_MSD,
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CLK_SD_SLOT,
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CLK_USB,
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CLK_SSP,
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};
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#define MCI_NAND *((volatile unsigned long *)(NAND_FLASH_BASE + 0x04))
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#define MCI_SD *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
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#if defined(SANSA_FUZE) || defined(SANSA_E200V2) || defined(SANSA_C200V2)
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#define DEBUG_DBOP
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#include "dbop-as3525.h"
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#endif
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static inline unsigned read_cp15 (void)
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{
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unsigned cp15_value;
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asm volatile (
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"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" : "=r"(cp15_value));
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return (cp15_value);
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}
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static int calc_freq(int clk)
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{
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unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3;
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unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf;
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unsigned int u_out_div;
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#if CONFIG_CPU == AS3525
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switch(clk) {
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/* clk_main = clk_int = 24MHz oscillator */
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case CLK_PLLA:
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if(CGU_PLLASUP & (1<<3))
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return 0;
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/*assume 24MHz oscillator only input available */
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u_out_div = ((CGU_PLLA>>13) & 0x3); /* bits 13:14 */
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if (u_out_div == 3) /* for 11 NO=4 */
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u_out_div=4;
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/* NO = 0 not allowed */
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return DIV_FINITE(((2 * (CGU_PLLA & 0xff))*CLK_MAIN),
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(((CGU_PLLA>>8) & 0x1f)*u_out_div));
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case CLK_PLLB:
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if(CGU_PLLBSUP & (1<<3))
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return 0;
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/*assume 24MHz oscillator only input available */
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u_out_div = ((CGU_PLLB>>13) & 0x3); /* bits 13:14 */
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if (u_out_div == 3) /* for 11 NO=4 */
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u_out_div=4;
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/* NO = 0 not allowed */
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return DIV_FINITE(((2 * (CGU_PLLB & 0xff))*CLK_MAIN),
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(((CGU_PLLB>>8) & 0x1f)*u_out_div));
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#else /* AS3525v2 */
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int od, f, r;
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/* AS3525v2 */
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switch(clk) {
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case CLK_PLLA:
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if(CGU_PLLASUP & (1<<3))
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return 0;
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f = (CGU_PLLA & 0x7F) + 1;
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r = ((CGU_PLLA >> 7) & 0x7) + 1;
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od = (CGU_PLLA >> 10) & 1 ? 2 : 1;
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return (CLK_MAIN / 2) * f / (r * od);
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case CLK_PLLB:
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if(CGU_PLLBSUP & (1<<3))
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return 0;
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f = (CGU_PLLB & 0x7F) + 1;
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r = ((CGU_PLLB >> 7) & 0x7) + 1;
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od = (CGU_PLLB >> 10) & 1 ? 2 : 1;
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return (CLK_MAIN / 2) * f / (r * od);
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case CLK_SD_SLOT:
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switch(CGU_SDSLOT & 3) {
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case 0:
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return CLK_MAIN/(((CGU_SDSLOT>>2)& 0xf)+1);
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case 1:
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return calc_freq(CLK_PLLA)/(((CGU_SDSLOT>>2)& 0xf)+1);
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case 2:
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return calc_freq(CLK_PLLB)/(((CGU_SDSLOT>>2)& 0xf)+1);
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default:
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return 0;
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}
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#endif /* CONFIG_CPU == AS3525 */
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case CLK_PROC:
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#if CONFIG_CPU == AS3525 /* not in arm926-ejs */
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if (!(read_cp15()>>30)) /* fastbus */
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return calc_freq(CLK_PCLK);
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else /* Synch or Asynch bus*/
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#endif /* CONFIG_CPU == AS3525 */
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return calc_freq(CLK_FCLK);
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case CLK_FCLK:
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switch(CGU_PROC & 3) {
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case 0:
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return (CLK_MAIN * (8 - prediv)) / (8 * (postdiv + 1));
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case 1:
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return (calc_freq(CLK_PLLA) * (8 - prediv)) /
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(8 * (postdiv + 1));
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case 2:
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return (calc_freq(CLK_PLLB) * (8 - prediv)) /
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(8 * (postdiv + 1));
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default:
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return 0;
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}
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case CLK_EXTMEM:
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#if CONFIG_CPU == AS3525
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switch(CGU_PERI & 3) {
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#else /* as3525v2 */
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/* bits 1:0 of CGU_PERI always read as 0 and source = FCLK */
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switch(3) {
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#endif /* CONFIG_CPU == AS3525 */
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case 0:
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return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
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case 1:
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return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1);
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case 2:
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return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
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case 3:
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default:
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return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
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}
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case CLK_PCLK:
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return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);
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case CLK_IDE:
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switch(CGU_IDE & 3) {
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case 0:
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return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1);
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case 1:
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return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1);
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case 2:
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return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1);
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default:
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return 0;
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}
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case CLK_I2C:
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ams_i2c_get_debug_cpsr(&u_out_div);
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/* NO = 0 not allowed */
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return DIV_FINITE(calc_freq(CLK_PCLK), (u_out_div));
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case CLK_I2SI:
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switch((CGU_AUDIO>>12) & 3) {
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case 0:
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return CLK_MAIN/(((CGU_AUDIO>>14) & 0x1ff)+1);
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case 1:
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return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>14) & 0x1ff)+1);
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case 2:
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return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>14) & 0x1ff)+1);
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default:
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return 0;
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}
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case CLK_I2SO:
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switch(CGU_AUDIO & 3) {
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case 0:
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return CLK_MAIN/(((CGU_AUDIO>>2) & 0x1ff)+1);
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case 1:
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return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>2) & 0x1ff)+1);
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case 2:
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return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>2) & 0x1ff)+1);
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default:
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return 0;
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}
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case CLK_DBOP:
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return calc_freq(CLK_PCLK)/((CGU_DBOP & 7)+1);
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#if CONFIG_CPU == AS3525
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case CLK_SD_MCLK_NAND:
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if(!(MCI_NAND & (1<<8)))
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return 0;
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else if(MCI_NAND & (1<<10))
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return calc_freq(CLK_IDE);
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else
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return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
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case CLK_SD_MCLK_MSD:
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if(!(MCI_SD & (1<<8)))
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return 0;
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else if(MCI_SD & (1<<10))
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return calc_freq(CLK_PCLK);
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else
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return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
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#else /* as3525v2 */
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case CLK_SSP:
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/* NO = 0 not allowed */
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return DIV_FINITE(calc_freq(CLK_PCLK), SSP_CPSR);
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#endif /* CONFIG_CPU == AS3525 */
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case CLK_USB:
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switch(CGU_USB & 3) { /* 0-> div=1 other->div=1/(2*n) */
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case 0:
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if (!((CGU_USB>>2) & 0x7))
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return CLK_MAIN;
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else
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return CLK_MAIN/(2*((CGU_USB>>2) & 0x7));
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case 1:
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if (!((CGU_USB>>2) & 0x7))
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return calc_freq(CLK_PLLA);
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else
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return calc_freq(CLK_PLLA)/(2*((CGU_USB>>2) & 0x7));
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case 2:
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if (!((CGU_USB>>2) & 0x7))
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return calc_freq(CLK_PLLB);
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else
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return calc_freq(CLK_PLLB)/(2*((CGU_USB>>2) & 0x7));
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default:
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return 0;
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}
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default:
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return 0;
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}
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}
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static bool dbg_btn(bool *done, int *x)
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{
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bool cont = !*done;
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if (cont)
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{
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lcd_update();
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int button = get_action(CONTEXT_STD,HZ/10);
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switch(button)
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{
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case DEBUG_CANCEL:
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*done = true;
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/*fallthrough*/
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case DEBUG_NEXT:
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cont = false;
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/*fallthrough*/
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case DEBUG_LEFT_JUSTIFY:
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(*x) = 0;
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sleep(HZ/5);
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break;
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case DEBUG_LEFT_SCROLL:
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(*x)--;
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break;
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default:
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break;
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}
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}
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lcd_clear_display();
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return cont;
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}
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bool dbg_hw_info(void)
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{
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int line;
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int x = 0;
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bool done = false;
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lcd_clear_display();
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lcd_setfont(FONT_SYSFIXED);
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while(!done)
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{
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while(dbg_btn(&done, &x))
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{
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#if defined(SANSA_C200V2) || defined(SANSA_FUZEV2) || \
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defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
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line = 0;
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lcd_puts(x, line++, "[Submodel:]");
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#if defined(SANSA_C200V2)
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lcd_putsf(x, line++, "C200v2 variant %d", c200v2_variant);
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#elif defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || \
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defined(SANSA_CLIPZIP)
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lcd_putsf(x, line++, "AMSv2 variant %d", amsv2_variant);
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#endif
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}
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while(dbg_btn(&done, &x))
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{
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#endif
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line = 0;
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lcd_puts(x, line++, "[Clock Frequencies:]");
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lcd_puts(x, line++, " SET ACTUAL");
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#if CONFIG_CPU == AS3525
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lcd_putsf(x, line++, "922T:%s %3dMHz",
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(!(read_cp15()>>30)) ? "FAST " :
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(read_cp15()>>31) ? "ASYNC" : "SYNC ",
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#else /* as3525v2 */
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lcd_putsf(x, line++, "926ejs: %3dMHz",
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#endif
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calc_freq(CLK_PROC)/D_MHZ);
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "PLLA", AS3525_PLLA_FREQ/D_MHZ,
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calc_freq(CLK_PLLA)/D_MHZ);
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lcd_putsf(x, line++, "PLLB: %3dMHz", calc_freq(CLK_PLLB)/D_MHZ);
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lcd_putsf(x, line++, "FCLK: %3dMHz", calc_freq(CLK_FCLK)/D_MHZ);
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "DRAM", AS3525_PCLK_FREQ/D_MHZ,
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calc_freq(CLK_EXTMEM)/D_MHZ);
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "PCLK", AS3525_PCLK_FREQ/D_MHZ,
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calc_freq(CLK_PCLK)/D_MHZ);
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#if LCD_HEIGHT < 176 /* clip */
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}
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while(dbg_btn(&done, &x))
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{
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line = 0;
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#endif /* LCD_HEIGHT < 176 */
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "IDE ", AS3525_IDE_FREQ/D_MHZ,
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calc_freq(CLK_IDE)/D_MHZ);
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "DBOP", AS3525_DBOP_FREQ/D_MHZ,
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calc_freq(CLK_DBOP)/D_MHZ);
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lcd_putsf(x, line++, "%s:%3dkHz %3dkHz", "I2C ", AS3525_I2C_FREQ/D_KHZ,
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calc_freq(CLK_I2C)/D_KHZ);
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lcd_putsf(x, line++, "I2SI: %s %3dMHz", (CGU_AUDIO & (1<<23)) ?
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"on " : "off" , calc_freq(CLK_I2SI)/D_MHZ);
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lcd_putsf(x, line++, "I2SO: %s %3dMHz", (CGU_AUDIO & (1<<11)) ?
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"on " : "off", calc_freq(CLK_I2SO)/D_MHZ);
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#if CONFIG_CPU == AS3525
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struct ams_sd_debug_info dbg;
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ams_sd_get_debug_info(&dbg);
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "SD ",
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((AS3525_IDE_FREQ/ D_MHZ) /
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((dbg.mci_nand & MCI_CLOCK_BYPASS)? 1:(((dbg.mci_nand & 0xff)+1) * 2))),
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calc_freq(CLK_SD_MCLK_NAND)/D_MHZ);
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#ifdef HAVE_MULTIDRIVE
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "uSD ",
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((AS3525_PCLK_FREQ/ D_MHZ) /
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((dbg.mci_sd & MCI_CLOCK_BYPASS) ? 1: (((dbg.mci_sd & 0xff) + 1) * 2))),
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calc_freq(CLK_SD_MCLK_MSD)/D_MHZ);
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#endif
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#else /*AS3525v2*/
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "SD ", AS3525_SDSLOT_FREQ/D_MHZ,
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calc_freq(CLK_SD_SLOT)/D_MHZ);
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long freq_ssp = calc_freq(CLK_SSP);
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if (freq_ssp >= D_MHZ)
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lcd_putsf(x, line++, "%s:%3dMHz %3dMHz", "SSP ", AS3525_SSP_FREQ/D_MHZ,
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calc_freq(CLK_SSP)/D_MHZ);
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else
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lcd_putsf(x, line++, "SSP :%3dMHz %3dkHz", AS3525_SSP_FREQ/D_MHZ,
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calc_freq(CLK_SSP)/D_KHZ);
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#endif /* CONFIG_CPU == AS3525 */
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lcd_putsf(x, line++, "USB : %3dMHz", calc_freq(CLK_USB)/D_MHZ);
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#if LCD_HEIGHT < 176 /* clip */
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}
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while(dbg_btn(&done, &x))
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{
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lcd_clear_display();
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line = 0;
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#endif /* LCD_HEIGHT < 176 */
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lcd_putsf(x, line++, "MMU : %s CVDDP:%4d", (read_cp15() & CP15_MMU) ?
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" on" : "off", adc_read(ADC_CVDD) * 25);
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lcd_putsf(x, line++, "Icache:%s Dcache:%s",
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(read_cp15() & CP15_IC) ? " on" : "off",
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(read_cp15() & CP15_DC) ? " on" : "off");
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}
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while(dbg_btn(&done, &x))
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{
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line = 0;
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lcd_putsf(x, line++, "CGU_PLLA :%8x", (unsigned int)(CGU_PLLA));
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lcd_putsf(x, line++, "CGU_PLLB :%8x", (unsigned int)(CGU_PLLB));
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lcd_putsf(x, line++, "CGU_PROC :%8x", (unsigned int)(CGU_PROC));
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lcd_putsf(x, line++, "CGU_PERI :%8x", (unsigned int)(CGU_PERI));
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lcd_putsf(x, line++, "CGU_IDE :%8x", (unsigned int)(CGU_IDE));
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lcd_putsf(x, line++, "CGU_DBOP :%8x", (unsigned int)(CGU_DBOP));
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lcd_putsf(x, line++, "CGU_AUDIO :%8x", (unsigned int)(CGU_AUDIO));
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lcd_putsf(x, line++, "CGU_USB :%8x", (unsigned int)(CGU_USB));
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#if LCD_HEIGHT < 176 /* clip */
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}
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while(dbg_btn(&done, &x))
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{
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line = 0;
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#endif /* LCD_HEIGHT < 176 */
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unsigned int i2c_cpsr;
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ams_i2c_get_debug_cpsr(&i2c_cpsr);
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lcd_putsf(x, line++, "I2C2_CPSR :%8x", i2c_cpsr);
|
|
#if CONFIG_CPU == AS3525
|
|
lcd_putsf(x, line++, "MCI_NAND :%8x", (unsigned int)(MCI_NAND));
|
|
lcd_putsf(x, line++, "MCI_SD :%8x", (unsigned int)(MCI_SD));
|
|
#else /* as3525v2 */
|
|
lcd_putsf(x, line++, "CGU_MEMSTK:%8x", (unsigned int)(CGU_MEMSTICK));
|
|
lcd_putsf(x, line++, "CGU_SDSLOT:%8x", (unsigned int)(CGU_SDSLOT));
|
|
#endif
|
|
lcd_putsf(x, line++, "SSP_CPSR :%8x", (unsigned int)(SSP_CPSR));
|
|
}
|
|
}
|
|
|
|
lcd_setfont(FONT_UI);
|
|
return false;
|
|
}
|
|
|
|
#if CONFIG_CPU == AS3525v2
|
|
void adc_set_voltage_mux(int channel)
|
|
{
|
|
ascodec_lock();
|
|
/*this register also controls which subregister is subsequently written, so be careful*/
|
|
ascodec_write(AS3543_PMU_ENABLE, 8 | channel << 4 );
|
|
ascodec_unlock();
|
|
}
|
|
#endif
|
|
|
|
bool dbg_ports(void)
|
|
{
|
|
int line, i;
|
|
int x = 0;
|
|
bool done = false;
|
|
lcd_clear_display();
|
|
lcd_setfont(FONT_SYSFIXED);
|
|
|
|
while(!done)
|
|
{
|
|
while(dbg_btn(&done, &x))
|
|
{
|
|
line = 0;
|
|
lcd_puts(x, line++, "[GPIO Vals and Dirs]");
|
|
lcd_putsf(x, line++, "%s: %2x DIR: %2x", "GPIOA", GPIOA_DATA, GPIOA_DIR);
|
|
lcd_putsf(x, line++, "%s: %2x DIR: %2x", "GPIOB", GPIOB_DATA, GPIOB_DIR);
|
|
lcd_putsf(x, line++, "%s: %2x DIR: %2x", "GPIOC", GPIOC_DATA, GPIOC_DIR);
|
|
lcd_putsf(x, line++, "%s: %2x DIR: %2x", "GPIOD", GPIOD_DATA, GPIOD_DIR);
|
|
lcd_putsf(x, line++, "CCU_IO:%8x", CCU_IO);
|
|
#ifdef DEBUG_DBOP
|
|
lcd_puts(x, line++, "[DBOP_DIN]");
|
|
lcd_putsf(x, line++, "DBOP_DIN: %4x", dbop_debug());
|
|
#endif
|
|
lcd_puts(x, line++, "[CP15]");
|
|
lcd_putsf(x, line++, "CP15: 0x%8x", read_cp15());
|
|
}
|
|
|
|
#if CONFIG_CPU == AS3525 /* as3525v2 channels are different */
|
|
#define BATTEMP_UNIT 5/2 /* 2.5mV */
|
|
static const char *adc_name[13] = {
|
|
"CHG_OUT ",
|
|
"RTCSUP ",
|
|
"VBUS ",
|
|
"CHG_IN ",
|
|
"CVDD ",
|
|
"BatTemp ",
|
|
"MicSup1 ",
|
|
"MicSup2 ",
|
|
"VBE1 ",
|
|
"VBE2 ",
|
|
"I_MicSup1",
|
|
"I_MicSup2",
|
|
"VBAT ",
|
|
};
|
|
#elif CONFIG_CPU == AS3525v2
|
|
#define BATTEMP_UNIT 2 /* 2mV */
|
|
static const char *adc_name[16] = {
|
|
"BVDD ",
|
|
"BVDDR ",
|
|
"CHGIN ",
|
|
"CHGOUT ",
|
|
"VBUS ",
|
|
NULL,
|
|
"BatTemp ",
|
|
NULL,
|
|
"MicSup ",
|
|
NULL,
|
|
"I_MiSsup",
|
|
NULL,
|
|
"VBE_1uA ",
|
|
"VBE_2uA ",
|
|
"I_CHGact",
|
|
"I_CHGref",
|
|
};
|
|
|
|
static const char *adc_mux_name[10] = {
|
|
NULL,
|
|
"AVDD27 ",
|
|
"AVDD17 ",
|
|
"PVDD1 ",
|
|
"PVDD2 ",
|
|
"CVDD1 ",
|
|
"CVDD2 ",
|
|
"RVDD ",
|
|
"FVDD ",
|
|
"PWGD ",
|
|
};
|
|
#endif
|
|
|
|
lcd_clear_display();
|
|
while(dbg_btn(&done, &x))
|
|
{
|
|
line = 0;
|
|
|
|
for(i=0; i<5; i++)
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_name[i], adc_read(i) * 5);
|
|
for(; i<8; i++)
|
|
if(adc_name[i])
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_name[i],
|
|
adc_read(i) * BATTEMP_UNIT);
|
|
#if LCD_HEIGHT < 176 /* clip */
|
|
}
|
|
while(dbg_btn(&done, &x))
|
|
{
|
|
line = 0;
|
|
#endif /* LCD_HEIGHT < 176 */
|
|
for(i=8; i<10; i++)
|
|
if(adc_name[i])
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_name[i], adc_read(i));
|
|
for(; i<12; i++)
|
|
if(adc_name[i])
|
|
lcd_putsf(x, line++, "%s: %d uA", adc_name[i], adc_read(i));
|
|
#if CONFIG_CPU == AS3525 /* different units */
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_name[i], adc_read(i)*5/2);
|
|
#elif CONFIG_CPU == AS3525v2
|
|
for(; i<16; i++)
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_name[i], adc_read(i));
|
|
#endif
|
|
}
|
|
#if CONFIG_CPU == AS3525v2 /*extend AS3543 voltage registers*/
|
|
while(dbg_btn(&done, &x))
|
|
{
|
|
line = 0;
|
|
for(i=1; i<9; i++){
|
|
adc_set_voltage_mux(i); /*change the voltage mux to a new channel*/
|
|
lcd_putsf(x, line++, "%s: %d mV", adc_mux_name[i], adc_read(5) * 5);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
lcd_setfont(FONT_UI);
|
|
return false;
|
|
}
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
|
/* Return CPU voltage setting in millivolts */
|
|
int get_cpu_voltage_setting(void)
|
|
{
|
|
int value;
|
|
|
|
#if CONFIG_CPU == AS3525
|
|
value = ascodec_read(AS3514_CVDD_DCDC3) & 0x3;
|
|
value = 1200 - value * 50;
|
|
#else /* as3525v2 */
|
|
value = ascodec_read_pmu(0x17, 1) & 0x7f;
|
|
|
|
/* Calculate in 0.1mV steps */
|
|
if (value == 0)
|
|
/* 0 volts */;
|
|
else if (value <= 0x40)
|
|
value = 6000 + value * 125;
|
|
else if (value <= 0x70)
|
|
value = 14000 + (value - 0x40) * 250;
|
|
else if (value <= 0x7f)
|
|
value = 26000 + (value - 0x70) * 500;
|
|
|
|
/* Return voltage setting in millivolts */
|
|
value = (value + 5) / 10;
|
|
#endif /* CONFIG_CPU */
|
|
|
|
return value;
|
|
}
|
|
#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
|