After conducting some simplistic tests, I found that the power usage
did not appear to be affected by the CPU frequency.
I tested by playing back a 44.1 KHz FLAC file on single track repeat,
and measured current with the AXP173's battery discharge current ADC.
The button and LCD backlights were set to always on. Headphones were
unplugged and the volume was muted to eliminate any influence from
the headphone amp.
On average the current usage was between 78-81 mA at 1008 MHz, 252 MHz,
and 112 MHz. If anything, 1008 MHz drew _less_ current than the lower
frequencies, by about 1-3 mA.
A possible explanation for this, assuming it's not just a bias of the
test, is that the CPU idle state saves so much power that it's better
to maximize the real time that the CPU spends idling. More systematic
testing is needed to confirm this.
Change-Id: I527473e8c4c12bc1e94f8d4e849fecc108022abe
There's no point including this in normal builds: the stats are not
used for anything, they are not really of interest to anyone except
developers, and add a small overhead to the kernel tick.
Change-Id: I1b4f67cc62d11d634a8cec279dca513dd10eea96
Initializing the clocks in the SPL brings Rockbox in line with
how the FiiO M3K's original SPL works. It's likely other X1000
devices do this too.
There was a logic error in the previous setup: the code falsely
assumed that DDR memory would always be running from MPLL, but
it would be switched to APLL by the bootloader. Rockbox would
then try to re-init APLL, albeit with the same parameters. Maybe
this was the cause of the boot hang on some units.
Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
What we really want is to avoid any interrupts being generated
before the drivers which handle them are properly initialized.
Intead of trashing all GPIOs, search for the problem pins and
fix them, leaving the others alone.
This fixes the M3K's button light flickering on boot and should
stop the M3K from entering a potentially confusing "dead" state
where all the lights are off but the CPU is still on.
Change-Id: I13a6da0f0950190396bff5d6e8c343c668e8fea1
SPL is now designed so core X1000 code is in control of the boot,
under the reasonable assumption that the device boots from flash.
It should not be too hard to adapt to other X1000 ports.
The biggest functional change is that the SPL can now read/write
the flash, under the control of a host computer. The SPL relies
on the boot ROM for USB communication, so the host has to execute
the SPL multiple times following a protocol.
Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
'Bugfix' mono_bitmap_part reads ahead in the buffer,
if the height is <= char bit pixels other memory gets read
Change-Id: I6e0d7a9017e1f9c371ffbd56af149ac20cb82341
Tested on eros q, everything measured from line out,
open circuit.
- volume steps were approximately double the dB they
were labelled as, so "-2 dB" would result in a change
of about -4 dB from maximum (0, +6.2dBV)
- maximum volume defining the line out volume only
changed every 10 values, and then was not close
to correct- "-10 dB" resulted in -2.5 dB from maximum
This gets the volume dB approximately correct, and
maximum volume correctly sets the line out volume.
I was unable to get odd values in the max volume
to work, so set the step size to 2 instead of one.
For "consumer level" (-10dBV), set to -16.
For "Pro level" (+4dBu -> ~1.8dBV), set to -4.
Change-Id: I898b85d768153579a893b23551019af88f865d21
It was just being used as a proxy "yeah, we called hw_init()" so
just use a flag for that directly.
affects rocker, erosq, xduoo x3ii/x20, and fiiom3klinux
Change-Id: I14bd9f8d91f1d6cc8de0982a7426e2a103c6bfce
Detection at startup is proving to be unreliable. Even if card is not
present at startup, upon insertion it will sort itself out properly.
Change-Id: I9ee90b724c90c530a39264f698c200a48aa72b1d
Including direct use of the external SD card mount
Known issue: If SD card is inserted at startup, it must be
ejected and reinserted to be registered.
Change-Id: I5f420160bda32135cbb088c1e8b04b6e3a73018e
(Don't include rbpaths.h in settings.h, or string-extra.h in rbpaths.h)
Build-tested on rocker, erosq, mini2g, nano2g,
xduoox3, clipzip, dx50, and uisim
Change-Id: If32e9c9910f5c8247a655cb64522b84d6d7ccbb5
The X3's line out is a bit hot, at ~4.3Vpp, so allow it to be backed off.
(On my X3, backing it off to -6dB brings Vpp down to ~3.4V)
Change-Id: Iea38ef1c6a1b183d0f8fb4eaf2bf9ed6b350a532
There is already a sound_numdecimals() function, according to Git
it's been around since 2005. No need to add another one :).
This reverts commit 92a0ab8789.
Change-Id: I533ebf1763dd7a27346842982493d4550f05ad7c
It turns out #include "settings.h" pulls in rbpaths.h which ends up
remapping open() to the path-mangling rockbox open().
By defining RB_FILESYSTEM_OS we prevent the remap. My mistake for not
testing this before committing!
Change-Id: I2978eb7b413693c4cb887b7ac7b2457780db7d25
With a full-scale 440Hz tone, the line out voltage
measured approx. 5.8Vpp at the 0 setting. WAY too hot!
(9 dBV, in fact)
For 0.894Vpp (-10 dBV - consumer devices), -18 appears to be
about right for line level signals, but for "pro" equipment
a different level may be desired.
Therefore, the user to cap the line out level by re-using the global
volume limit setting.
Change-Id: I0d1d6482ea95537e9a2d00884eaee2713771c614
Inline assembly in RoLO and the FiiO M3K bootloader used 'jr' to
jump to a newly loaded Rockbox binary, but incorrectly left the
branch delay slot open. That gives GCC an opening to place illegal
instrutions, etc, which might cause an unhandled exception.
Change-Id: Ia7a561fe530e94a41189d25f18a767c448177960
- Proper error codes are now returned from all functions. These codes will
be used by a host-side flash tool for error reporting.
- nand_erase_block() was replaced by nand_erase_bytes(). The caller can't
know how big an eraseblock is with the current API, so next best thing
is to verify the correct alignment inside the call and reject the erase
if it isn't properly aligned.
- Fixed typo in nandcmd_block_erase() which would cause an SFC error to be
interpreted as success. Yikes.
Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
Ensure the default setting reflects what the service manual says the
official battery capacity is. Change the ranges to reflect what
replacement batteries are actually available.
This range is actually much shorter in reality due to these units
requiring the rarer 3 pin battery type that uses a thermistor. As such
there's only one real replacement battery for each.
So the HDD1630 caps out around 700 mah while the HDD6330 caps out around
680 mah.
Change-Id: I2dbbba83ad2cd6e1d84e3481c4af84a06c45e16b
headphone ADC thread stack was slightly too small. Bump it up a bit.
(it was _perfectly_ sized for the prior older toolchain+optimization flags...)
Change-Id: I2ca67c2b85c54f879892a31e281d7696f893389c
Use of IF_COP_CORE was mistakenly introduced as part of 89acde6af2,
effectively short-circuiting multiple tests resulting in the code
paths always being executed, on both cores.
Use the correct macro, so per-CPU paths are handled properly.
Change-Id: Id346cf759fc1b06b7d56694d7af1f469caf785a4
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Enable its use in the jz47xx MIPS targets.
(accidently committed g#3249 before making these changes)
Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
This is just a minor cleanup of Solomon Peachy's code, and using
per-filesystem buffers instead of a single static buffer.
Tested and working on the FiiO M3K.
Change-Id: I3c19e8cc24e2f8aa07668c9d1c6d63364815050a
This uses the new unicode string literal feature that is available
now to greatly simplify the initialization of these special string
types. This makes them much more readable at a quick glance.
Change-Id: Iad8b49aa763486608e3bb7e83fb8abfb48ce0a7b
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all processors that define MEM_ALIGN_ATTR
Change-Id: I11edaab183b91a6d158f1f439f173b9b699dc914
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all arm processors
assign the default framebuffer to the default_vp as well
Change-Id: I0b76c30f2ddb5d6d2f7c6a132e4081aee58da17b
