Michael Sevakis
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a1ab7a55ff
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Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657
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2008-12-04 15:06:48 +00:00 |
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Daniel Stenberg
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2acc0ac542
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Updated our source code header to explicitly mention that we are GPL v2 or
later. We still need to hunt down snippets used that are not. 1324 modified
files...
http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
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2008-06-28 18:10:04 +00:00 |
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Karl Kurbjun
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0220a5fbc3
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Fix the ARM assembly to ensure that the stack is not used.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17443 a1c6a512-1295-4272-9138-f99709370657
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2008-05-10 18:30:46 +00:00 |
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Karl Kurbjun
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7510335fc4
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This is a big chunk of code necessary to prepare for Gigabeat F flash loading and and implementation of rolo. There should be no noticible changes for the user. A new bootloader is not needed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17213 a1c6a512-1295-4272-9138-f99709370657
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2008-04-22 04:34:25 +00:00 |
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Michael Sevakis
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99a65dfc1e
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Cache functions should include data and instruction barriers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17150 a1c6a512-1295-4272-9138-f99709370657
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2008-04-17 00:07:06 +00:00 |
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Michael Sevakis
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fb643c3f34
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Use real ARM 11 instructions for cache operations. Probably will factor out later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17131 a1c6a512-1295-4272-9138-f99709370657
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2008-04-15 21:38:29 +00:00 |
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Karl Kurbjun
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5a9a2b7bc4
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Unify the Gigabeat F/X and M:Robe MMU code while enabling it for the M:Robe
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15275 a1c6a512-1295-4272-9138-f99709370657
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2007-10-23 03:29:15 +00:00 |
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