When read it returns all enabled interrupt sources
When written it enables interrupt sources for each bit set
So just like VIC_INT_EN_CLEAR, we don't have to read the previous value
before writing to it (VIC_INT_EN_CLEAR is write-only anyway)
Thanks to Fred Bauer for spotting
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23734 a1c6a512-1295-4272-9138-f99709370657
of the CH_CONTROL and CH_CONFIGURATION registers easier to follow.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23725 a1c6a512-1295-4272-9138-f99709370657
DMAC_INT_TC_CLEAR is a write-only reg
HIGH bits of DMAC_SYNC mean synchronisation logic disabled.
Also, according to the OF and to tests, all the peripherals we use run at the same frequency (PCLK?).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20643 a1c6a512-1295-4272-9138-f99709370657
Retry blocks transfer if a problem happened
Remove unneeded blocking API from DMA code
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19714 a1c6a512-1295-4272-9138-f99709370657
Add dma_retain() and dma_release() to reference count the users
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19344 a1c6a512-1295-4272-9138-f99709370657
* Adds a callback to be called on end of transfer
* Add a function to disable a channel
* Services the 2 channels if both are active in the isr
SD driver: panics on error
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19333 a1c6a512-1295-4272-9138-f99709370657
