Rafaël Carré
d556f26820
as3525: use DMA for recording
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Flyspray: FS#11257
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25980 a1c6a512-1295-4272-9138-f99709370657
2010-05-13 05:26:12 +00:00
Rafaël Carré
f6ae574ac6
s5l870x : use mmu-arm.S
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:59:49 +00:00
Rafaël Carré
635de60ff3
mmu-arm.S: comment out dump_dcache_range()
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It is only used by gigabeats, and is defined in mmu-armv6.S already
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25630 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:22:01 +00:00
Rafaël Carré
96e97987d9
mmu-arm.S: disable MMU functions on CPUs which don't use them
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25629 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:17:08 +00:00
Rafaël Carré
4205a508d7
mmu-arm.S: Use correct implementations on arm926ej-s CPUs
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clean_dcache and invalidate_dcache were incorrect and too tied to the
arm920t/arm922t 64-way set associative caches
Make those functions smaller on as3525, as this CPU has a smaller cache
than the gigabeat F/X
Flyspray: FS#11106
Authors: Jack Halpin and myself
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25628 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:04:55 +00:00
Rafaël Carré
2f97effab9
mmu-arm* : cpucache_invalidate() needs to be in IRAM for rolo
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25627 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:29:37 +00:00
Rafaël Carré
208dc249e6
mmu-arm (v4/v5) : fix previous commit, clean/invalidate correctly the first segment in each loop
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25626 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:15:37 +00:00
Rafaël Carré
a0e1e329f7
mmu-arm (v4/v5) : use one less instruction in invalidate_dcache/clean_dcache
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25625 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:12:54 +00:00
Rafaël Carré
735b522929
Split ARMv6 code from mmu-arm.S
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23244 a1c6a512-1295-4272-9138-f99709370657
2009-10-18 13:07:14 +00:00
Michael Sparmann
3ac50ca9ff
Fix S5L870x cache coherency functions. They were split into a different file, as changes were needed all over the place.
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
2009-10-17 23:06:45 +00:00
Michael Sparmann
a931acd3ab
Added S5L870X cache coherency support
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23058 a1c6a512-1295-4272-9138-f99709370657
2009-10-09 21:41:57 +00:00
Michael Sevakis
63e709c7c8
Refine the routines in mmu-arm.c and move them to mmu-arm.S since the code is now 100% assembly.
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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19980 a1c6a512-1295-4272-9138-f99709370657
2009-02-11 23:56:00 +00:00
