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3 commits

Author SHA1 Message Date
Amaury Pouly
51cce81cd4 headergen_v2: add two new macros to write a raw write to set/clr variants
These macros are like jz_setf but instead of writing fields, they write a
raw value directly: jz_set(REG, value) and jz_clr(REG, value).

Change-Id: I660f20dd691b26d367533877875fc3226a26c992
2017-01-24 15:25:14 +01:00
Amaury Pouly
7b1bcae879 regtools: rename error_t to err_t to avoid name clash
Change-Id: Ib8d34e4f58f3225b1dafc533ce7e1b7867ad053b
2016-09-21 00:31:12 +01:00
Amaury Pouly
e62203aac1 regtools: add headergen_v2
This new header generator works differently from the previous one:
- it uses the new format
- the generated macro follow a different style (see below)
- the generated macro are highly documented!
- it supports SCT-style platform or RMW-style ones

Compared to the old style, the new one generate a big set of macros per
register/field/enum (loosely related to iohw.h from Embedded C spec). The user
then calls generic (names are customizable) macros to perform operations:

reg_read(REG_A)
reg_read(REG_B(3))
reg_read_field(REG_A, FIELD_X)
reg_read_field(REG_B(3), COOL_FIELD)
reg_write(REG_A, 0x42)
reg_write_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ))
reg_write_fielc(REG_B(3), COOL_FIELD_V(I_AM_COOL), BLA(42))

the following use RMW or SET/CLR variants, depending on target:
reg_set_field(REG_A, FLAG_U, FLAG_V)
reg_clr_field(REG_A, FIELD_X, FIELD_Y, IRQ)
reg_clr_field(REG_B(3), COOL_FIELD, BLA)

the following does clear followed by set, on SET/CLR targets:
reg_cs(REG_A, 0xff, 0x42)
reg_cs(REG_B(3), 0xaa, 0x55)
reg_cs_field(REG_A, FIELD_X(1), FIELD_Y(3), IRQ_V(FIQ))
reg_cs_field(REG_B(3), COOL_FIELD_V(I_AM_COOL))

The generator code is pretty long but has lots of documentation and lots of
macro names can be customized.

Change-Id: I5d6c5ec2406e58b5da11a5240c3a409a5bb5239a
2016-05-25 00:11:07 +01:00