NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
Rework the irq code, to put more code in the C part. When interrupt
nesting is enable, Rockbox gets pretty unstable so disable it for now.
Change-Id: Iee18b539c80ea408273f6082975faaa87d3ee1b6
The hardware watchdog automatically shutdown the device after 10s of
inactivity, being defined as 10s without the tick IRQ fired (aka braindead
device).
The software IRQ mechanism is more interesting: it uses a very high priority
timer setup as one-shot to trigger after 5s of inactivity (but IRQ still
enabled). When detected, it patches the running code to insert a SWI
instruction so that on interrupt return it will trigger a SWI and produce
a meaningfull backtrace to debug the deadlock. This should allow to debug
freezes in IRQ context.
Change-Id: Ic55dad01201676bfb6dd79e78e535c6707cb88e6
Rewrite IRQ handling to allow nested IRQs: on each IRQ entry, we save the
parameters on the (IRQ) stack and then switch to SVC mode (with its own
stack) and renable interrupts. Make sure interrupt is properly acknowledged
by using the read side-effect (RSE) mode and handle priority levels as well.
Change-Id: I3fd68289b430c56bdd256868939238ff268e42b4
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
The icoll code now has an IRQ storm detection mechanism which
will prevent the device from hard freezing in case it happen.
Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c
