The old max dma transfer size was set to 2^15 because allowing
values up to 2^16 would result in overflow of the transfer count
in many places. This was a problem with the old register headers
because the macros didn't make sure the result is contained in
the bitmask of the field. The new macro do so 2^16 will actually
end up being 0 which means 2^16 for the hardware. This is kind of
hacky but it works and I prefer that this stays a power of two
because setting it to 2^16-1 would be extremely weird.
Change-Id: I9ce5661c477a79ab52efd5c573948e2353117804
Add finer granularity to start command: now commands can be
prepared, schedule and semaphore increased independently.
Change-Id: Ib1ed1f20f4b46dc61b6dbab6ddec8b54e3d832b9
Reduce DMA maximum transfer size since transfering 64Kb requires
to set a size of 0 and it's not worth adding checks everywhere
to handle this special case. Also add statistics about unaligned
transfer (wrt to cache). Update debug screen accordingly and
simplify it so it can fit smaller screens too.
Change-Id: I18391702f5e100a21f6f8d1ebab28d9f2bd8c66f
Because DMA descriptors needs to be committed and discarded from
the cache, if they are not cache aligned and/or if their size
is not a multiple of cache ligne, nasty side effects could occur
with adjacents data. The same applies to DMA buffers which are
still potentially broken. Add a macro to ensure that these
constraints will not break by error in the future.
Change-Id: I1dd69a5a9c29796c156d953eaa57c0d281e79846
