Commit graph

13 commits

Author SHA1 Message Date
Solomon Peachy
0cb162a76b mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
2020-09-03 15:34:28 -04:00
Solomon Peachy
f913829d06 xduoox3: Disable the LCD and MSC0 clocks as we don't use them
Change-Id: If2261aed464fcbe3ea1f036dd18376fa8ff42e69
2020-09-02 16:59:13 +00:00
Solomon Peachy
5e335f5c33 jz4760: do the MSC (ie SD) clocking setup when we change PLL0
Change-Id: Ia17b1d7069af507c3f029bcaed0f65e7e97df275
2020-08-29 00:29:25 -04:00
Solomon Peachy
0aa2197d93 jz4760: SD driver enhancements:
* Check to see if clock is [not] running prior to [en|dis]abling it
 * Stop clock _prior_ to resetting controller
 * Stop clock after transaction is completed, not before initiating it
 * Use controller's low power mode (disables clocks when idle)
 * Fix, and enable, interrupt-driven DMA transfers
 * Fixes for full interrupt-driven operation  (WIP, still broken)

Change-Id: I723ffa6450fc85f97898c8a8b3e538ae31c4858e
2020-08-25 12:07:50 -04:00
Solomon Peachy
63ef81de31 jz4760: Give each SD interface its own DMA channel, semaphore, and mutex
* Allows both SD interfaces to have requests in flight simultaneously
 * Fixed a deadlock in the hotswap code
 * Ensure TX DMA is idle before initiating a request (bug due to a typo)

Change-Id: I988fa29df5f8e41fc6bbdcc517db89842003b34d
2020-08-25 12:16:33 +00:00
Solomon Peachy
eb0e41c1cc jz4760: Support dynamic reclocking!
default/low speed is 192 MHz, Max is 576

Downclock PCLK/MCLK/etc to 96MHz to save a bit of juice

Honestly the high speed could be dialed down to, eg 384
as this thing is so bloody fast..

Change-Id: Ie65597c74290f1603e65f69dae8e75b59c8ba0b4
2020-08-07 11:42:45 -04:00
Solomon Peachy
83963fcb15 XduooX3: Uncomment code that prevented hotswap from working.
Change-Id: I5efec00e60aacf05166407ad43b9d63340e18967
2019-07-29 11:14:41 -04:00
Solomon Peachy
1e076a7be8 jz7460: Disable IRQ-driven DMA transfers.
This greatly increases the stability of SD card write operations.

(I suspect the underlying problem is not IRQ operation itself, instead
 being exacerbated by it..)

Change-Id: Ia00f0656abd4b3cb0b1b5fc9db7c1b6a02847956
2019-06-02 13:09:19 +02:00
Solomon Peachy
640ada0389 jz4760: Enhancements and fixes to SD driver.
* Fully Interrupt-driven, with proper task yielding
 * Much more robust error handling
 * Eliminate duplicate code
 * Pile of bugfixes

 (Much of this adapted from Igor Poretsky's tree)

Change-Id: I46006412323cba2088b70094635d62a241be1d7e
2018-09-20 19:38:25 -04:00
Solomon Peachy
1020897794 jz7640: SD driver improvements:
* Better multidrive support
 * Common slot1/slot2 handling code

Change-Id: Id0aed90cbba4246fdc71b42e03f016f8060d258a
2018-09-20 18:59:19 -04:00
Solomon Peachy
679a0bd193 jz74x0: MSC clock needs to be divided from PLL clock.
Change-Id: I0cf2f0d55e0859f896afef289e833935d7c5a599
2018-09-20 18:59:19 -04:00
Solomon Peachy
72820d8b2d jz4760: Greatly enhance debug code and silence some compilation warnings.
Change-Id: I1746d67c818ad099edea83e6242ffd5c79be0000
2018-09-20 18:59:19 -04:00
Solomon Peachy
0662793ca0 Add cleaned-up xDuoo X3 support
Cleaned up, rebased, and forward-ported from the xvortex fork.

(original credit to vsoftster@gmail.com)

Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
2018-07-28 10:56:31 -04:00