It turns out #include "settings.h" pulls in rbpaths.h which ends up
remapping open() to the path-mangling rockbox open().
By defining RB_FILESYSTEM_OS we prevent the remap. My mistake for not
testing this before committing!
Change-Id: I2978eb7b413693c4cb887b7ac7b2457780db7d25
With a full-scale 440Hz tone, the line out voltage
measured approx. 5.8Vpp at the 0 setting. WAY too hot!
(9 dBV, in fact)
For 0.894Vpp (-10 dBV - consumer devices), -18 appears to be
about right for line level signals, but for "pro" equipment
a different level may be desired.
Therefore, the user to cap the line out level by re-using the global
volume limit setting.
Change-Id: I0d1d6482ea95537e9a2d00884eaee2713771c614
Inline assembly in RoLO and the FiiO M3K bootloader used 'jr' to
jump to a newly loaded Rockbox binary, but incorrectly left the
branch delay slot open. That gives GCC an opening to place illegal
instrutions, etc, which might cause an unhandled exception.
Change-Id: Ia7a561fe530e94a41189d25f18a767c448177960
The viewport used for the scrollbar is allocated on the stack, and falls
out of scope before the next call to set_viewport(), which sets a flag
in the now-out-of-scope "last" viewport.
Change-Id: I2c8bfcff500d189fa3857411aadc2e16aa545d2c
- Proper error codes are now returned from all functions. These codes will
be used by a host-side flash tool for error reporting.
- nand_erase_block() was replaced by nand_erase_bytes(). The caller can't
know how big an eraseblock is with the current API, so next best thing
is to verify the correct alignment inside the call and reject the erase
if it isn't properly aligned.
- Fixed typo in nandcmd_block_erase() which would cause an SFC error to be
interpreted as success. Yikes.
Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
Tested on ErosQ
Added a setting in the Advanced Softlock menu to always
have autolock on, rather than having to "arm" it with the
softlock button. Lock/Unlock still works the same with
this on, but when the screen turns off, the device always
ends up in the locked state. Requires Autolock On to be
set as well, and the normal Autolock functionality is
unchanged with this off.
Caveat: the power/softlock button must be pressed
at least once after powering on the device or enabling the
feature. After that, it should consistently always "arm"
the autolock.
Added feature to manual in
manual/configure_rockbox/system_options.tex. Also updated
some labels I had changed in the Advanced Key Lock menu
and added information for Disable All Lock Notifications
in a previous commit. Shared items also updated in
manual/configure_rockbox/display_options.tex for selective
backlight.
Change-Id: I09dc6814bee803e40c7088157e1fe9d01d5f3474
Ensure the default setting reflects what the service manual says the
official battery capacity is. Change the ranges to reflect what
replacement batteries are actually available.
This range is actually much shorter in reality due to these units
requiring the rarer 3 pin battery type that uses a thermistor. As such
there's only one real replacement battery for each.
So the HDD1630 caps out around 700 mah while the HDD6330 caps out around
680 mah.
Change-Id: I2dbbba83ad2cd6e1d84e3481c4af84a06c45e16b
Will allow the QuickScreen to be accessed in the playlist catalogue
and when editing a playlist using the playlist viewer.
Change-Id: I4b7108db6384eb2077ffdccb2992f2e51a39f42f
headphone ADC thread stack was slightly too small. Bump it up a bit.
(it was _perfectly_ sized for the prior older toolchain+optimization flags...)
Change-Id: I2ca67c2b85c54f879892a31e281d7696f893389c
Instead of 'ifdef ENABLEPLUGINS' (which always gets set) use
'ifeq(yes,$(ENABLEPLUGINS))' which means any value other than 'yes' is
treated as a negative.
Change-Id: I6c92eef5565328f1bb9f64a4d379dec697354224
Use of IF_COP_CORE was mistakenly introduced as part of 89acde6af2,
effectively short-circuiting multiple tests resulting in the code
paths always being executed, on both cores.
Use the correct macro, so per-CPU paths are handled properly.
Change-Id: Id346cf759fc1b06b7d56694d7af1f469caf785a4
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Note: It's marked as 'unusable' right now, so it won't show up
on build.rockbox.org, nor will daily & voice files be
created.
Change-Id: I5ea133477a6b4c0296c46757d0375994ad812cc5
Enable its use in the jz47xx MIPS targets.
(accidently committed g#3249 before making these changes)
Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
This is just a minor cleanup of Solomon Peachy's code, and using
per-filesystem buffers instead of a single static buffer.
Tested and working on the FiiO M3K.
Change-Id: I3c19e8cc24e2f8aa07668c9d1c6d63364815050a
Text entry keymap was almost completely backwards, and it was
impossible to submit without adding one last character.
Change-Id: I40a224fe20e228c5e4670dd6583318918c59c827
This uses the new unicode string literal feature that is available
now to greatly simplify the initialization of these special string
types. This makes them much more readable at a quick glance.
Change-Id: Iad8b49aa763486608e3bb7e83fb8abfb48ce0a7b
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all processors that define MEM_ALIGN_ATTR
Change-Id: I11edaab183b91a6d158f1f439f173b9b699dc914
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all arm processors
assign the default framebuffer to the default_vp as well
Change-Id: I0b76c30f2ddb5d6d2f7c6a132e4081aee58da17b
