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Add some defines for pp502x. No guarantee as to full accuracy yet but that's not really too important. Use them in the code.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14912 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2007-09-30 10:53:31 +00:00
parent 1ed54f4302
commit e760ba5a04
3 changed files with 73 additions and 40 deletions
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72
firmware/export/pp5020.h
View file

@ -38,6 +38,7 @@
#define COP_MESSAGE (*(volatile unsigned long *)(0x60001004)) #define COP_MESSAGE (*(volatile unsigned long *)(0x60001004))
#define CPU_REPLY (*(volatile unsigned long *)(0x60001008)) #define CPU_REPLY (*(volatile unsigned long *)(0x60001008))
#define COP_REPLY (*(volatile unsigned long *)(0x6000100c)) #define COP_REPLY (*(volatile unsigned long *)(0x6000100c))
#define MBOX_CONTROL (*(volatile unsigned long *)(0x60001010))
/* Interrupts */ /* Interrupts */
#define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000)) #define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000))
@ -170,12 +171,24 @@
*/ */
/* Cache Control */ /* Cache Control */
#define CACHE_PRIORITY (*(volatile unsigned long *)(0x60006044))
#define CACHE_CTL (*(volatile unsigned long *)(0x6000c000)) #define CACHE_CTL (*(volatile unsigned long *)(0x6000c000))
#define CACHE_MASK (*(volatile unsigned long *)(0xf000f040))
#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f044))
#define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
/* CACHE_CTL bits */
#define CACHE_CTL_DISABLE 0x0000
#define CACHE_CTL_ENABLE 0x0001
#define CACHE_CTL_RUN 0x0002
#define CACHE_CTL_INIT 0x0004
#define CACHE_CTL_VECT_REMAP 0x0010
#define CACHE_CTL_READY 0x4000
#define CACHE_CTL_BUSY 0x8000
/* CACHE_OPERATION bits */
#define CACHE_OP_FLUSH 0x0002
#define CACHE_OP_INVALIDATE 0x0004
#define CACHE_DISABLE 0
#define CACHE_ENABLE 1
#define CACHE_RUN 2
#define CACHE_INIT 4
/* GPIO Ports */ /* GPIO Ports */
#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) #define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
@ -280,9 +293,17 @@
/* Device initialization */ /* Device initialization */
#define PP_VER1 (*(volatile unsigned long *)(0x70000000)) #define PP_VER1 (*(volatile unsigned long *)(0x70000000))
#define PP_VER2 (*(volatile unsigned long *)(0x70000004)) #define PP_VER2 (*(volatile unsigned long *)(0x70000004))
#define STRAP_OPT_A (*(volatile unsigned long *)(0x70000008))
#define STRAP_OPT_B (*(volatile unsigned long *)(0x7000000c))
#define BUS_WIDTH_MASK 0x00000010
#define RAM_TYPE_MASK 0x000000c0
#define ROM_TYPE_MASK 0x00000008
#define DEV_INIT (*(volatile unsigned long *)(0x70000020)) #define DEV_INIT (*(volatile unsigned long *)(0x70000020))
/* some timing that needs to be handled during clock setup */ /* some timing that needs to be handled during clock setup */
#define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034)) #define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
#define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038))
#define XMB_RAM_CFG (*(volatile unsigned long *)(0x7000003c))
#define INIT_USB 0x80000000 #define INIT_USB 0x80000000
@ -324,19 +345,32 @@
#define FIREWIRE_BASE 0xc6000000 #define FIREWIRE_BASE 0xc6000000
/* Memory controller */ /* Memory controller */
#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000)) #define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
#define CACHE_INIT_BASE (*(volatile unsigned long*)(0xf0004000)) /* 0xf0000000-0xf0001fff */
#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000)) #define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000))
#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000)) /* 0xf0002000-0xf0003fff */
#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) #define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000))
#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) /* 0xf0004000-0xf0007fff */
#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) #define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c)) #define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010)) #define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014)) #define MMAP_FIRST (*(volatile unsigned long*)(0xf000f000))
#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) #define MMAP_LAST (*(volatile unsigned long*)(0xf000f03c))
#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
#define CACHE_CTRL1 (*(volatile unsigned long*)(0xf000f020)) #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
#define CACHE_CTRL2 (*(volatile unsigned long*)(0xf000f024)) #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
#define MMAP4_LOGICAL (*(volatile unsigned long*)(0xf000f020))
#define MMAP4_PHYSICAL (*(volatile unsigned long*)(0xf000f024))
#define MMAP5_LOGICAL (*(volatile unsigned long*)(0xf000f028))
#define MMAP5_PHYSICAL (*(volatile unsigned long*)(0xf000f02c))
#define MMAP6_LOGICAL (*(volatile unsigned long*)(0xf000f030))
#define MMAP6_PHYSICAL (*(volatile unsigned long*)(0xf000f034))
#define MMAP7_LOGICAL (*(volatile unsigned long*)(0xf000f038))
#define MMAP7_PHYSICAL (*(volatile unsigned long*)(0xf000f03c))
#endif #endif /* __PP5020_H__ */

14
firmware/rolo.c
View file

@ -74,7 +74,7 @@ void rolo_restart_cop(void)
invalidate_icache(); invalidate_icache();
/* Disable cache */ /* Disable cache */
CACHE_CTL = CACHE_DISABLE; CACHE_CTL = CACHE_CTL_DISABLE;
/* Tell the main core that we're ready to reload */ /* Tell the main core that we're ready to reload */
cpu_reply = 1; cpu_reply = 1;
@ -123,9 +123,6 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
{ {
long i; long i;
unsigned char* localdest = dest; unsigned char* localdest = dest;
#ifdef CPU_PP502x
unsigned long* memmapregs = (unsigned long*)0xf000f000;
#endif
/* This is the equivalent of a call to memcpy() but this must be done from /* This is the equivalent of a call to memcpy() but this must be done from
iram to avoid overwriting itself and we don't want to depend on memcpy() iram to avoid overwriting itself and we don't want to depend on memcpy()
@ -148,11 +145,14 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
flush_icache(); flush_icache();
/* Disable cache */ /* Disable cache */
CACHE_CTL = CACHE_DISABLE; CACHE_CTL = CACHE_CTL_DISABLE;
/* Reset the memory mapping registers to zero */ /* Reset the memory mapping registers to zero */
for (i=0;i<8;i++) {
memmapregs[i]=0; volatile unsigned long *mmap_reg;
for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
*mmap_reg = 0;
}
#if NUM_CORES > 1 #if NUM_CORES > 1
/* Tell the COP it's safe to continue rebooting */ /* Tell the COP it's safe to continue rebooting */

27
firmware/target/arm/system-pp502x.c
View file

@ -86,21 +86,21 @@ void irq(void)
void flush_icache(void) ICODE_ATTR; void flush_icache(void) ICODE_ATTR;
void flush_icache(void) void flush_icache(void)
{ {
if (CACHE_CTL & CACHE_ENABLE) if (CACHE_CTL & CACHE_CTL_ENABLE)
{ {
outl(inl(0xf000f044) | 0x2, 0xf000f044); CACHE_OPERATION |= CACHE_OP_FLUSH;
while ((CACHE_CTL & 0x8000) != 0); while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
} }
} }
void invalidate_icache(void) ICODE_ATTR; void invalidate_icache(void) ICODE_ATTR;
void invalidate_icache(void) void invalidate_icache(void)
{ {
if (CACHE_CTL & CACHE_ENABLE) if (CACHE_CTL & CACHE_CTL_ENABLE)
{ {
unsigned i; unsigned i;
outl(inl(0xf000f044) | 0x6, 0xf000f044); CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
while ((CACHE_CTL & 0x8000) != 0); while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
for (i = 0x10000000; i < 0x10002000; i += 16) for (i = 0x10000000; i < 0x10002000; i += 16)
inb(i); inb(i);
} }
@ -112,17 +112,16 @@ static void init_cache(void)
unsigned i; unsigned i;
/* cache init mode? */ /* cache init mode? */
CACHE_CTL |= CACHE_INIT; CACHE_CTL |= CACHE_CTL_INIT;
/* what's this do? */ /* what's this do? */
outl(inl(0x60006044) | (CURRENT_CORE == CPU ? 0x10 : 0x20), CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
0x60006044);
outl(0xc00, 0xf000f040); CACHE_MASK = 0xc00;
outl(0xfc0, 0xf000f044); CACHE_OPERATION = 0xfc0;
/* enable cache */ /* enable cache */
CACHE_CTL |= CACHE_INIT | CACHE_ENABLE | CACHE_RUN; CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
/* fill cache from physical address - do we have a better candidate for /* fill cache from physical address - do we have a better candidate for
an 8KB unchanging memory range? */ an 8KB unchanging memory range? */
@ -285,14 +284,14 @@ void system_reboot(void)
{ {
/* Reboot */ /* Reboot */
#ifdef SANSA_C200 #ifdef SANSA_C200
CACHE_CTL &= ~0x10; CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
pp_i2c_send( 0x46, 0x23, 0x0); /* backlight off */ pp_i2c_send( 0x46, 0x23, 0x0); /* backlight off */
/* Magic used by the c200 OF: 0x23066000 /* Magic used by the c200 OF: 0x23066000
Magic used by the c200 BL: 0x23066b7b Magic used by the c200 BL: 0x23066b7b
In both cases, the OF executes these 2 commands from iram. */ In both cases, the OF executes these 2 commands from iram. */
outl(0x23066b7b, 0x70000008); outl(0x23066b7b, STRAP_OPT_A);
DEV_RS = DEV_SYSTEM; DEV_RS = DEV_SYSTEM;
#else #else
DEV_RS |= DEV_SYSTEM; DEV_RS |= DEV_SYSTEM;