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Split up DMA and ATA, but don't enable it (yet).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17386 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2008-05-05 15:47:26 +00:00
parent 6d12109ef7
commit e025cb1c38
5 changed files with 187 additions and 73 deletions
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3
firmware/SOURCES
View file

@ -721,8 +721,9 @@ target/arm/ata-as-arm.S
target/arm/lcd-as-memframe.S
target/arm/mmu-arm.c
target/arm/tms320dm320/creative-zvm/adc-creativezvm.c
target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c
target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
target/arm/tms320dm320/creative-zvm/dma-creativezvm.c
target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c
target/arm/tms320dm320/creative-zvm/pcm-creativezvm.c
target/arm/tms320dm320/creative-zvm/pic-creativezvm.c
target/arm/tms320dm320/creative-zvm/power-creativezvm.c

70
firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
View file

@ -92,79 +92,9 @@ bool ata_is_coldstart(void)
return true;
}
#if 0 /* Disabled as device crashes; probably due to SDRAM addresses aren't 32-bit aligned */
#define CS1_START 0x50000000
#define DEST_ADDR (ATA_IOBASE-CS1_START)
static struct wakeup transfer_completion_signal;
void MTC0(void)
{
IO_INTC_IRQ1 = 1 << IRQ_MTC0;
wakeup_signal(&transfer_completion_signal);
}
void copy_read_sectors(unsigned char* buf, int wordcount)
{
bool lasthalfword = false;
unsigned short tmp;
if(wordcount < 16)
{
_copy_read_sectors(buf, wordcount);
return;
}
else if((unsigned long)buf % 32) /* Not 32-byte aligned */
{
unsigned char* bufend = buf + ((unsigned long)buf % 32);
if( ((unsigned long)buf % 32) % 2 )
lasthalfword = true;
wordcount -= ((unsigned long)buf % 32) / 2;
do
{
tmp = ATA_DATA;
*buf++ = tmp >> 8;
*buf++ = tmp & 0xff;
} while (buf < bufend); /* tail loop is faster */
}
IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */
IO_EMIF_AHBADDH = ((unsigned)buf >> 16) & ~(1 << 15); /* Set variable address */
IO_EMIF_AHBADDL = (unsigned)buf & 0xFFFF;
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
IO_EMIF_DMASIZE = wordcount*2;
IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */
//wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
while(IO_EMIF_DMACTL & 1)
nop;
if(lasthalfword)
{
*buf += wordcount * 2;
tmp = ATA_DATA;
*buf++ = tmp >> 8;
*buf++ = tmp & 0xff;
}
}
void copy_write_sectors(const unsigned char* buf, int wordcount)
{
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_SDRAM_SDDMASEL = 0x0820; /* Temporarily set to standard value */
IO_EMIF_AHBADDH = ((int)buf >> 16) & ~(1 << 15); /* Set variable address */
IO_EMIF_AHBADDL = (int)buf & 0xFFFF;
IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
IO_EMIF_DMASIZE = wordcount;
IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
}
#endif
void ata_device_init(void)
{
IO_INTC_EINT1 |= INTR_EINT1_EXT2; /* enable GIO2 interrupt */
#if 0
IO_INTC_EINT1 |= 1 << IRQ_MTC0; /* enable MTC interrupt */
wakeup_init(&transfer_completion_signal);
#endif
//TODO: mimic OF inits...
return;
}

9
firmware/target/arm/tms320dm320/creative-zvm/ata-target.h
View file

@ -20,10 +20,15 @@
#ifndef ATA_TARGET_H
#define ATA_TARGET_H
/* ASM optimized reading and writing */
/* DMA optimized reading and writing */
#define ATA_OPTIMIZED_READING
#define ATA_OPTIMIZED_WRITING
void copy_read_sectors(unsigned char* buf, int wordcount);
/*
#include "dma-target.h"
#define copy_read_sectors dma_ata_read
#define copy_write_sectors dma_ata_write
*/
void copy_read_sectors(const unsigned char* buf, int wordcount);
void copy_write_sectors(const unsigned char* buf, int wordcount);
/* General purpose memory region #1 */

150
firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c Normal file
View file

@ -0,0 +1,150 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2008 by Maurus Cuelenaere
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "kernel.h"
#include "thread.h"
#include "system.h"
#include "dma-target.h"
#include "dm320.h"
#include "ata-target.h"
#include <stdbool.h>
#define CS1_START 0x50000000
#define CS2_START 0x60000000
#define SDRAM_START 0x00900000
#define FLASH_START 0x00100000
#define CF_START 0x40000000
#define SSFDC_START 0x48000000
static struct wakeup transfer_completion_signal;
static bool dma_in_progress = false;
static int debugi = 0;
static void debugj(char* mes)
{
lcd_puts(0,debugi++,mes);
lcd_update();
}
void MTC0(void)
{
IO_INTC_IRQ1 = INTR_IRQ1_MTC0;
wakeup_signal(&transfer_completion_signal);
dma_in_progress = false;
}
void dma_start(const void* addr, size_t size)
{
/* Compatibility with Gigabeat S in dma_start.c */
(void) addr;
(void) size;
}
#define ATA_DEST (ATA_IOBASE-CS1_START)
void dma_ata_read(unsigned char* buf, int shortcount)
{
char mes[30];
snprintf(mes, 30, "read(0x%x, %d)", buf, shortcount);
debugj(mes);
if(dma_in_progress)
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
if((unsigned long)buf & 0x1F)
debugj(" aligning");
while((unsigned long)buf & 0x1F)
{
unsigned short tmp;
tmp = ATA_DATA;
*buf++ = tmp & 0xFF;
*buf++ = tmp >> 8;
shortcount--;
}
if (!shortcount)
return;
IO_SDRAM_SDDMASEL = 0x0820; /* 32-byte burst mode transfer */
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & 0x7FFF; /* Set variable address */
IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF;
IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF;
IO_EMIF_DMASIZE = shortcount/2; /* 16-bits *2 = 1 word */
IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */
dma_in_progress = true;
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
int i;
for(i = 0; i < 30; i++)
{
if(*buf++ != 0)
mes[i] = *buf;
}
debugj(mes);
if(shortcount % 2)
{
debugj(" aligning");
unsigned short tmp;
tmp = ATA_DATA;
*buf++ = tmp & 0xFF;
*buf++ = tmp >> 8;
}
}
void dma_ata_write(unsigned char* buf, int wordcount)
{
if(dma_in_progress)
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
while((unsigned long)buf & 0x1F)
{
unsigned short tmp;
tmp = (unsigned short) *buf++;
tmp |= (unsigned short) *buf++ << 8;
SET_16BITREG(ATA_DATA, tmp);
wordcount--;
}
if (!wordcount)
return;
IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & ~(1 << 15); /* Set variable address */
IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF;
IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF;
IO_EMIF_DMASIZE = (wordcount+1)/2;
IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */
dma_in_progress = true;
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
}
void dma_init(void)
{
IO_INTC_EINT1 |= INTR_EINT1_MTC0; /* enable MTC interrupt */
wakeup_init(&transfer_completion_signal);
dma_in_progress = false;
}

28
firmware/target/arm/tms320dm320/creative-zvm/dma-target.h Normal file
View file

@ -0,0 +1,28 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2008 by Maurus Cuelenaere
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef DMA_TARGET_H
#define DMA_TARGET_H
void dma_start(const void* addr, size_t size); /* Compatibility with Gigabeat S in dma_start.c */
void dma_ata_read(unsigned char* buf, int wordcount);
void dma_ata_write(unsigned char* buf, int wordcount);
void dma_init(void);
#endif