First check in
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@93 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Björn Stenberg
parent
11d0198e49
commit
d42d78fe4b
6 changed files with 1939 additions and 0 deletions
32
gdb/Makefile
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32
gdb/Makefile
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@ -0,0 +1,32 @@
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# __________ __ ___.
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# Open \______ \ ____ ____ | | _\_ |__ _______ ___
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# Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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# Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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# Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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# \/ \/ \/ \/ \/
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# $Id$
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#
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TARGET = stub
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OBJS = start.o sh-stub.o
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#LIBS = -L/home/linus/sh1/lib/gcc-lib/sh-elf/3.0.4 -lgcc
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LIBS = -lgcc
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.s.o:
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sh-elf-as -o $@ $<
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.c.o:
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sh-elf-gcc -O -m1 -Wall -c -o $@ $<
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$(TARGET).out: $(TARGET).elf
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sh-elf-objcopy -O binary $(TARGET).elf $(TARGET).out
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scramble $(TARGET).out archos.mod
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$(TARGET).elf: $(OBJS)
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sh-elf-gcc -nostartfiles $(OBJS) -lgcc -Wl,-Map,$(TARGET).map -o $(TARGET).elf -Tlinker.cfg
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clean:
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rm $(OBJS) $(TARGET).map $(TARGET).elf $(TARGET).out archos.mod
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start.o: start.s
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stub.o: stub.c
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s-stub.o: sh-stub.c
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24
gdb/archos.h
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24
gdb/archos.h
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@ -0,0 +1,24 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef ARCHOS_H
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#define ARCHOS_H
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#define SYSCLOCK 12000000
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#endif
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27
gdb/linker.cfg
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27
gdb/linker.cfg
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@ -0,0 +1,27 @@
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ENTRY(_start)
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OUTPUT_FORMAT(elf32-sh)
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SECTIONS
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{
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.vectors 0x09000000 :
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{
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*(.vectors);
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. = ALIGN(0x200);
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start.o(.text)
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*(.rodata)
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}
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.bss :
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{
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_stack = . + 0x1000;
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}
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.text :
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{
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*(.text)
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}
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.pad 0x0900C800 :
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{
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LONG(0);
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}
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}
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1628
gdb/sh-stub.c
Normal file
1628
gdb/sh-stub.c
Normal file
File diff suppressed because it is too large
Load diff
187
gdb/sh.h
Normal file
187
gdb/sh.h
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@ -0,0 +1,187 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SH_H_INCLUDED
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#define SH_H_INCLUDED
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/* Support for Serial I/O using on chip uart */
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#define SMR0 (*(volatile unsigned char *)(0x05FFFEC0)) /* Ch 0 serial mode */
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#define BRR0 (*(volatile unsigned char *)(0x05FFFEC1)) /* Ch 0 bit rate */
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#define SCR0 (*(volatile unsigned char *)(0x05FFFEC2)) /* Ch 0 serial ctrl */
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#define TDR0 (*(volatile unsigned char *)(0x05FFFEC3)) /* Ch 0 transmit data */
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#define SSR0 (*(volatile unsigned char *)(0x05FFFEC4)) /* Ch 0 serial status */
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#define RDR0 (*(volatile unsigned char *)(0x05FFFEC5)) /* Ch 0 receive data */
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#define SMR1 (*(volatile unsigned char *)(0x05FFFEC8)) /* Ch 1 serial mode */
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#define BRR1 (*(volatile unsigned char *)(0x05FFFEC9)) /* Ch 1 bit rate */
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#define SCR1 (*(volatile unsigned char *)(0x05FFFECA)) /* Ch 1 serial ctrl */
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#define TDR1 (*(volatile unsigned char *)(0x05FFFECB)) /* Ch 1 transmit data */
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#define SSR1 (*(volatile unsigned char *)(0x05FFFECC)) /* Ch 1 serial status */
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#define RDR1 (*(volatile unsigned char *)(0x05FFFECD)) /* Ch 1 receive data */
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/*
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* Serial mode register bits
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*/
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#define SYNC_MODE 0x80
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#define SEVEN_BIT_DATA 0x40
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#define PARITY_ON 0x20
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#define ODD_PARITY 0x10
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#define STOP_BITS_2 0x08
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#define ENABLE_MULTIP 0x04
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#define PHI_64 0x03
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#define PHI_16 0x02
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#define PHI_4 0x01
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/*
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* Serial control register bits
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*/
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#define SCI_TIE 0x80 /* Transmit interrupt enable */
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#define SCI_RIE 0x40 /* Receive interrupt enable */
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#define SCI_TE 0x20 /* Transmit enable */
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#define SCI_RE 0x10 /* Receive enable */
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#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
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#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
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#define SCI_CKE1 0x02 /* Clock enable 1 */
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#define SCI_CKE0 0x01 /* Clock enable 0 */
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/*
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* Serial status register bits
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*/
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#define SCI_TDRE 0x80 /* Transmit data register empty */
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#define SCI_RDRF 0x40 /* Receive data register full */
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#define SCI_ORER 0x20 /* Overrun error */
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#define SCI_FER 0x10 /* Framing error */
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#define SCI_PER 0x08 /* Parity error */
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#define SCI_TEND 0x04 /* Transmit end */
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#define SCI_MPB 0x02 /* Multiprocessor bit */
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#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
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/*
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* Port Registers
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*/
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#define PADR (*(volatile unsigned short *)(0x5ffffc0)) /* Port A Data */
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#define PAIOR (*(volatile unsigned short *)(0x5ffffc4)) /* Port A I/O */
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#define PACR1 (*(volatile unsigned short *)(0x5ffffc8)) /* Port A ctrl 1 */
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#define PACR2 (*(volatile unsigned short *)(0x5ffffca)) /* Port A ctrl 2 */
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#define PBDR (*(volatile unsigned short *)(0x5ffffc2)) /* Port B Data */
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#define PBIOR (*(volatile unsigned short *)(0x5ffffc6)) /* Port B I/O */
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#define PBCR1 (*(volatile unsigned short *)(0x5ffffcc)) /* Port B ctrl 1 */
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#define PBCR2 (*(volatile unsigned short *)(0x5ffffce)) /* Port B ctrl 2 */
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#define CASCR (*(volatile unsigned short *)(0x5ffffee)) /* CAS strobe pin */
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#define PB15MD PB15MD1|PB14MD0
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#define PB14MD PB14MD1|PB14MD0
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#define PB13MD PB13MD1|PB13MD0
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#define PB12MD PB12MD1|PB12MD0
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#define PB11MD PB11MD1|PB11MD0
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#define PB10MD PB10MD1|PB10MD0
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#define PB9MD PB9MD1|PB9MD0
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#define PB8MD PB8MD1|PB8MD0
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#define PB_TXD1 PB11MD1
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#define PB_RXD1 PB10MD1
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#define PB_TXD0 PB9MD1
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#define PB_RXD0 PB8MD1
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#define PB7MD PB7MD1|PB7MD0
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#define PB6MD PB6MD1|PB6MD0
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#define PB5MD PB5MD1|PB5MD0
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#define PB4MD PB4MD1|PB4MD0
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#define PB3MD PB3MD1|PB3MD0
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#define PB2MD PB2MD1|PB2MD0
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#define PB1MD PB1MD1|PB1MD0
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#define PB0MD PB0MD1|PB0MD0
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/* Bus state controller registers */
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#define BCR (*(volatile unsigned short *)(0x5ffffa0)) /* Bus control */
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#define WCR1 (*(volatile unsigned short *)(0x5ffffa2)) /* Wait state ctrl 1 */
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#define WCR2 (*(volatile unsigned short *)(0x5ffffa4)) /* Wait state ctrl 2 */
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#define WCR3 (*(volatile unsigned short *)(0x5ffffa6)) /* Wait state ctrl 3 */
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#define DCR (*(volatile unsigned short *)(0x5ffffa8)) /* DRAM area ctrl */
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#define PCR (*(volatile unsigned short *)(0x5ffffaa)) /* Parity control */
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#define RCR (*(volatile unsigned short *)(0x5ffffae)) /* Refresh control */
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#define RTCSR (*(volatile unsigned short *)(0x5ffffae)) /* Refresh timer
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control/status */
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#define RTCNT (*(volatile unsigned short *)(0x5ffffb0)) /* Refresh timer cnt */
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#define RTCOR (*(volatile unsigned short *)(0x5ffffb2)) /* Refresh time
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constant */
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/* Interrupt controller registers */
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#define IPRA (*(volatile unsigned short *)(0x5ffff84)) /* Priority A */
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#define IPRB (*(volatile unsigned short *)(0x5ffff86)) /* Priority B */
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#define IPRC (*(volatile unsigned short *)(0x5ffff88)) /* Priority C */
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#define IPRD (*(volatile unsigned short *)(0x5ffff88)) /* Priority D */
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#define IPRE (*(volatile unsigned short *)(0x5ffff8c)) /* Priority E */
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#define ICR (*(volatile unsigned short *)(0x5ffff8e)) /* Interrupt Control */
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/* ITU registers */
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#define TSTR (*(volatile unsigned char *)(0x5ffff00)) /* Timer Start */
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#define TSNC (*(volatile unsigned char *)(0x5ffff01)) /* Timer Synchro */
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||||||
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#define TMDR (*(volatile unsigned char *)(0x5ffff02)) /* Timer Mode */
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||||||
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#define TFCR (*(volatile unsigned char *)(0x5ffff03)) /* Timer Function Ctrl */
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||||||
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#define TOCR (*(volatile unsigned char *)(0x5ffff31)) /* Timer Output Ctrl */
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||||||
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#define TCR0 (*(volatile unsigned char *)(0x5ffff04)) /* Timer 0 Ctrl */
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#define TIOR0 (*(volatile unsigned char *)(0x5ffff05)) /* Timer 0 I/O Ctrl */
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#define TIER0 (*(volatile unsigned char *)(0x5ffff06)) /* Timer 0 Int Enable */
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||||||
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#define TSR0 (*(volatile unsigned char *)(0x5ffff07)) /* Timer 0 Status */
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||||||
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#define TCNT0 (*(volatile unsigned short *)(0x5ffff08)) /* Timer 0 Count */
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||||||
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#define GRA0 (*(volatile unsigned short *)(0x5ffff0a)) /* Timer 0 GRA */
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||||||
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#define GRB0 (*(volatile unsigned short *)(0x5ffff0c)) /* Timer 0 GRB */
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||||||
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#define TCR1 (*(volatile unsigned char *)(0x5ffff0e)) /* Timer 1 Ctrl */
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||||||
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#define TIOR1 (*(volatile unsigned char *)(0x5ffff0f)) /* Timer 1 I/O Ctrl */
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||||||
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#define TIER1 (*(volatile unsigned char *)(0x5ffff10)) /* Timer 1 Int Enable */
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||||||
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#define TSR1 (*(volatile unsigned char *)(0x5ffff11)) /* Timer 1 Status */
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||||||
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#define TCNT1 (*(volatile unsigned short *)(0x5ffff12)) /* Timer 1 Count */
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||||||
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#define GRA1 (*(volatile unsigned short *)(0x5ffff14)) /* Timer 1 GRA */
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||||||
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#define GRB1 (*(volatile unsigned short *)(0x5ffff16)) /* Timer 1 GRB */
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||||||
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||||||
|
#define TCR2 (*(volatile unsigned char *)(0x5ffff18)) /* Timer 2 Ctrl */
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||||||
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#define TIOR2 (*(volatile unsigned char *)(0x5ffff19)) /* Timer 2 I/O Ctrl */
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||||||
|
#define TIER2 (*(volatile unsigned char *)(0x5ffff1a)) /* Timer 2 Int Enable */
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||||||
|
#define TSR2 (*(volatile unsigned char *)(0x5ffff1b)) /* Timer 2 Status */
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||||||
|
#define TCNT2 (*(volatile unsigned short *)(0x5ffff1c)) /* Timer 2 Count */
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||||||
|
#define GRA2 (*(volatile unsigned short *)(0x5ffff1e)) /* Timer 2 GRA */
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||||||
|
#define GRB2 (*(volatile unsigned short *)(0x5ffff20)) /* Timer 2 GRB */
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||||||
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||||||
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#define TCR3 (*(volatile unsigned char *)(0x5ffff22)) /* Timer 3 Ctrl */
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||||||
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#define TIOR3 (*(volatile unsigned char *)(0x5ffff23)) /* Timer 3 I/O Ctrl */
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||||||
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#define TIER3 (*(volatile unsigned char *)(0x5ffff24)) /* Timer 3 Int Enable */
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||||||
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#define TSR3 (*(volatile unsigned char *)(0x5ffff25)) /* Timer 3 Status */
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||||||
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#define TCNT3 (*(volatile unsigned short *)(0x5ffff26)) /* Timer 3 Count */
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||||||
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#define GRA3 (*(volatile unsigned short *)(0x5ffff28)) /* Timer 3 GRA */
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||||||
|
#define GRB3 (*(volatile unsigned short *)(0x5ffff2a)) /* Timer 3 GRB */
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||||||
|
#define BRA3 (*(volatile unsigned short *)(0x5ffff2c)) /* Timer 3 BRA */
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||||||
|
#define BRB3 (*(volatile unsigned short *)(0x5ffff2e)) /* Timer 3 BRB */
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||||||
|
|
||||||
|
#define TCR4 (*(volatile unsigned char *)(0x5ffff32)) /* Timer 4 Ctrl */
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||||||
|
#define TIOR4 (*(volatile unsigned char *)(0x5ffff33)) /* Timer 4 I/O Ctrl */
|
||||||
|
#define TIER4 (*(volatile unsigned char *)(0x5ffff34)) /* Timer 4 Int Enable */
|
||||||
|
#define TSR4 (*(volatile unsigned char *)(0x5ffff35)) /* Timer 4 Status */
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||||||
|
#define TCNT4 (*(volatile unsigned short *)(0x5ffff36)) /* Timer 4 Count */
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||||||
|
#define GRA4 (*(volatile unsigned short *)(0x5ffff38)) /* Timer 4 GRA */
|
||||||
|
#define GRB4 (*(volatile unsigned short *)(0x5ffff3a)) /* Timer 4 GRB */
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||||||
|
#define BRA4 (*(volatile unsigned short *)(0x5ffff3c)) /* Timer 4 BRA */
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||||||
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#define BRB4 (*(volatile unsigned short *)(0x5ffff3e)) /* Timer 4 BRB */
|
||||||
|
|
||||||
|
#endif
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||||||
41
gdb/start.s
Normal file
41
gdb/start.s
Normal file
|
|
@ -0,0 +1,41 @@
|
||||||
|
!***************************************************************************
|
||||||
|
! __________ __ ___.
|
||||||
|
! Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||||
|
! Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||||
|
! Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
|
! Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
|
! \/ \/ \/ \/ \/
|
||||||
|
! $Id$
|
||||||
|
!
|
||||||
|
! Copyright (C) 2002 by Linus Nielsen Feltzing
|
||||||
|
!
|
||||||
|
! All files in this archive are subject to the GNU General Public License.
|
||||||
|
! See the file COPYING in the source tree root for full license agreement.
|
||||||
|
!
|
||||||
|
! This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||||
|
! KIND, either express or implied.
|
||||||
|
!
|
||||||
|
!***************************************************************************
|
||||||
|
! note: sh-1 has a "delay cycle" after every branch where you can
|
||||||
|
! execute another instruction "for free".
|
||||||
|
|
||||||
|
.file "start.s"
|
||||||
|
.section .text
|
||||||
|
.extern _INIT
|
||||||
|
.extern _vectable
|
||||||
|
.extern _init_stack
|
||||||
|
.global _start
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
_start:
|
||||||
|
mov.l 1f, r1
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||||||
|
mov.l 3f, r3
|
||||||
|
mov.l 2f, r15
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||||||
|
jmp @r3
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||||||
|
ldc r1, vbr
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||||||
|
nop
|
||||||
|
|
||||||
|
1: .long _vectable
|
||||||
|
2: .long _init_stack+2*1024*4
|
||||||
|
3: .long _INIT
|
||||||
|
.type _start,@function
|
||||||
Loading…
Reference in a new issue