S5L870x: Fix PCLK freq

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23103 a1c6a512-1295-4272-9138-f99709370657

firmware/target/arm/s5l8700/crt0.S

@@ -123,7 +123,7 @@ start_loc:
     ldr r0, [r1,#0x20]  // PLLLOCK
     tst r0, #1
     beq 1b
-    mov r0, #0x80
+    mov r0, #0x280
     str r0, [r1,#0x3c]  // CLKCON2
     ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
     str r0, [r1]        // CLKCON

firmware/target/arm/s5l8700/kernel-s5l8700.c

@@ -37,7 +37,7 @@ void INT_TIMERB(void)
 
 void tick_start(unsigned int interval_in_ms)
 {
-    int cycles = 10 * interval_in_ms;
+    int cycles = 5 * interval_in_ms;
     
     /* enable timer clock */
     PWRCON &= ~(1 << 4);

firmware/target/arm/s5l8700/timer-s5l8700.c

@@ -31,8 +31,6 @@
     The S5L8700 timer resolution is only 16-bit. Larger counts are done by using
     both the clock-select and the clock prescaler to bring the count down into
     the range of the 16-bit counter.
-    
-    TODO: investigate why the timer seems to count twice as fast as expected
 */
 
 void INT_TIMERC(void)