Sansa Connect: Revise codec initialization/shutdown.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31149 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Tomasz Moń
parent
4811b516a3
commit
bac6a70184
6 changed files with 219 additions and 73 deletions
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@ -23,11 +23,6 @@
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#include "system.h"
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#include "string.h"
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#include "audio.h"
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#ifdef SANSA_CONNECT
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#include "avr-sansaconnect.h"
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#endif
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#if CONFIG_I2C == I2C_DM320
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#include "i2c-dm320.h"
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#endif
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@ -84,11 +79,41 @@ static void aic3x_write_reg(unsigned reg, unsigned value)
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}
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}
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static unsigned char aic3x_read_reg(unsigned reg)
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{
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unsigned char data;
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#if CONFIG_I2C == I2C_DM320
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if (i2c_read_bytes(AIC3X_ADDR, reg, &data, 1))
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#else
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#warning Implement aic3x_read_reg()
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#endif
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{
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logf("AIC3X read error reg=0x%0x", reg);
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data = 0;
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}
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return data;
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}
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static void aic3x_change_reg(unsigned reg, unsigned char or_mask,
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unsigned char and_mask)
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{
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unsigned char data;
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data = aic3x_read_reg(reg);
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data &= and_mask;
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data |= or_mask;
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aic3x_write_reg(reg, data);
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}
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static void aic3x_apply_volume(void)
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{
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unsigned char data[3];
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#if 0 /* handle page switching onve we use first page at all */
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#if 0 /* handle page switching once we use first page at all */
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aic3x_write_reg(0, 0); /* switch to page 0 */
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#endif
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@ -113,11 +138,29 @@ static void audiohw_mute(bool mute)
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{
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if (mute)
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{
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/* DAC_L1 routed to HPLOUT, mute */
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aic3x_write_reg(AIC3X_DAC_L1_VOL, 0xF6);
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/* DAC_R1 routed to HPROUT, mute */
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aic3x_write_reg(AIC3X_DAC_R1_VOL, 0xF6);
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/* DAC_L1 routed to MONO_LOP/M, mute */
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aic3x_write_reg(AIC3X_DAC_L1_MONO_LOP_M_VOL, 0xF6);
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/* DAC_R1 routed to MONO_LOP/M, mute */
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aic3x_write_reg(AIC3X_DAC_R1_MONO_LOP_M_VOL, 0xF6);
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volume_left |= 0x80;
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volume_right |= 0x80;
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}
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else
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{
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/* DAC_L1 routed to HPLOUT, volume analog gain 0xC (-6.0dB) */
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aic3x_write_reg(AIC3X_DAC_L1_VOL, 0x8C);
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/* DAC_R1 routed to HPROUT, volume analog gain 0xC (-6.0 dB) */
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aic3x_write_reg(AIC3X_DAC_R1_VOL, 0x8C);
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/* DAC_L1 routed to MONO_LOP/M, gain 0x2 (-1.0dB) */
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aic3x_write_reg(AIC3X_DAC_L1_MONO_LOP_M_VOL, 0x92);
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/* DAC_R1 routed to MONO_LOP/M, gain 0x2 (-1.0dB) */
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aic3x_write_reg(AIC3X_DAC_R1_MONO_LOP_M_VOL, 0x92);
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volume_left &= 0x7F;
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volume_right &= 0x7F;
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}
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@ -137,8 +180,51 @@ void audiohw_init(void)
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/* Do software reset (self-clearing) */
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aic3x_write_reg(AIC3X_SOFT_RESET, 0x80);
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/* ADC fs = fs(ref)/5.5; DAC fs = fs(ref) */
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aic3x_write_reg(AIC3X_SMPL_RATE, 0x90);
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/* driver power-on time 200 ms, ramp-up step time 4 ms */
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aic3x_write_reg(AIC3X_POP_REDUCT, 0x7C);
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/* Output common-move voltage 1.35V, disable LINE2[LR] bypass */
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/* Output soft-stepping = one step per fs */
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aic3x_write_reg(AIC3X_POWER_OUT, 0x00);
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/* Audio data interface */
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/* GPIO1 used for audio serial data bus ADC word clock */
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aic3x_write_reg(AIC3X_GPIO1_CTRL, 0x10);
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/* BCLK and WCLK are outputs (master mode) */
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aic3x_write_reg(AIC3X_DATA_REG_A, 0xC0);
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/* right-justified mode */
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aic3x_write_reg(AIC3X_DATA_REG_B, 0x80);
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/* data offset = 0 clocks */
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aic3x_write_reg(AIC3X_DATA_REG_C, 0);
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/* Left DAC plays left channel, Right DAC plays right channel */
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aic3x_write_reg(AIC3X_DATAPATH, 0xA);
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/* power left and right DAC, HPLCOM constant VCM output */
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aic3x_write_reg(AIC3X_DAC_POWER, 0xD0);
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/* HPRCOM as constant VCM output. Enable short-circuit protection
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(limit current) */
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aic3x_write_reg(AIC3X_HIGH_POWER, 0xC);
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/* DAC_L1 routed to HPLOUT */
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aic3x_write_reg(AIC3X_DAC_L1_VOL, 0x80);
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/* DAC_R1 routed to HPROUT */
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aic3x_write_reg(AIC3X_DAC_R1_VOL, 0x80);
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/* DAC_L1 routed to MONO_LOP/M */
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aic3x_write_reg(AIC3X_DAC_L1_MONO_LOP_M_VOL, 0x80);
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/* DAC_R1 routed to MONO_LOP/M */
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aic3x_write_reg(AIC3X_DAC_R1_MONO_LOP_M_VOL, 0x80);
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/* DAC_L1 routed to LEFT_LOP/M */
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aic3x_write_reg(AIC3X_DAC_L1_LEFT_LOP_M_VOL, 0x80);
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/* DAC_R1 routed to RIGHT_LOP/M */
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aic3x_write_reg(AIC3X_DAC_R1_RIGHT_LOP_M_VOL, 0x80);
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/* LEFT_LOP/M output level 0dB, not muted */
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aic3x_write_reg(AIC3X_LEFT_LOP_M_LVL, 0x8);
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/* RIGHT_LOP/M output level 0dB, not muted */
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aic3x_write_reg(AIC3X_RIGHT_LOP_M_LVL, 0x8);
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/* Enable PLL. Set Q=16, P=1 */
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aic3x_write_reg(AIC3X_PLL_REG_A, 0x81);
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@ -146,69 +232,36 @@ void audiohw_init(void)
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aic3x_write_reg(AIC3X_PLL_REG_B, 0xD4);
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/* PLL D = 5211 */
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aic3x_write_reg(AIC3X_PLL_REG_C, 0x51);
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aic3x_write_reg(AIC3X_PLL_REG_D, 0x6C); /* PLL D = 5211 */
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aic3x_write_reg(AIC3X_PLL_REG_D, 0x6C);
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/* PLL R = 1 */
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aic3x_write_reg(AIC3X_OVERFLOW, 0x01);
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/* Left DAC plays left channel, Right DAC plays right channel */
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aic3x_write_reg(AIC3X_DATAPATH, 0xA);
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/* ADC fs = fs(ref)/5.5; DAC fs = fs(ref) */
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aic3x_write_reg(AIC3X_SMPL_RATE, 0x90);
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/* Audio data interface */
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/* BCLK and WCLK are outputs (master mode) */
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aic3x_write_reg(AIC3X_DATA_REG_A, 0xC0);
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/* right-justified mode */
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aic3x_write_reg(AIC3X_DATA_REG_B, 0x80);
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/* data offset = 0 clocks */
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aic3x_write_reg(AIC3X_DATA_REG_C, 0);
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/* GPIO1 used for audio serial data bus ADC word clock */
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aic3x_write_reg(AIC3X_GPIO1_CTRL, 0x10);
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/* HPLOUT output level 0dB, muted, high impedance */
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aic3x_write_reg(AIC3X_HPLOUT_LVL, 0x04);
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/* HPROUT output level 0dB, muted, high impedance */
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aic3x_write_reg(AIC3X_HPROUT_LVL, 0x04);
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/* power left and right DAC, HPLCOM constant VCM output */
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aic3x_write_reg(AIC3X_DAC_POWER, 0xD0);
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/* HPRCOM as constant VCM output. Enable short-circuit protection
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(limit current) */
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aic3x_write_reg(AIC3X_HIGH_POWER, 0xC);
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/* driver power-on time 200 ms, ramp-up step time 4 ms */
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aic3x_write_reg(AIC3X_POP_REDUCT, 0x7C);
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/* DAC_L1 routed to HPLOUT, volume analog gain 0xC (-6.0dB) */
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aic3x_write_reg(AIC3X_DAC_L1_VOL, 0x8C);
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/* HPLOUT output level 0dB, not muted, fully powered up */
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aic3x_write_reg(AIC3X_HPLOUT_LVL, 0xB);
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/* HPLCOM is muted */
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aic3x_write_reg(AIC3X_HPLCOM_LVL, 0x7);
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/* DAC_R1 routed to HPROUT, volume analog gain 0xC (-6.0 dB) */
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aic3x_write_reg(AIC3X_DAC_R1_VOL, 0x8C);
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/* HPROUT output level 0dB, not muted, fully powered up */
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aic3x_write_reg(AIC3X_HPROUT_LVL, 0xB);
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/* DAC_L1 routed to MONO_LOP/M, gain 0x2 (-1.0dB) */
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aic3x_write_reg(AIC3X_DAC_L1_MONO_LOP_M_VOL, 0x92);
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/* DAC_R1 routed to MONO_LOP/M, gain 0x2 (-1.0dB) */
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aic3x_write_reg(AIC3X_DAC_R1_MONO_LOP_M_VOL, 0x92);
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/* MONO_LOP output level 6dB, not muted, fully powered up */
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aic3x_write_reg(AIC3X_MONO_LOP_M_LVL, 0x6b);
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/* DAC_L1 routed to LEFT_LOP/M */
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aic3x_write_reg(AIC3X_DAC_L1_LEFT_LOP_M_VOL, 0x80);
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/* LEFT_LOP/M output level 0dB, not muted */
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aic3x_write_reg(AIC3X_LEFT_LOP_M_LVL, 0xB);
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/* DAC_R1 routed to RIGHT_LOP/M */
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aic3x_write_reg(AIC3X_DAC_R1_RIGHT_LOP_M_VOL, 0x80);
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/* RIGHT_LOP/M output level 0dB, not muted */
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aic3x_write_reg(AIC3X_RIGHT_LOP_M_LVL, 0xB);
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/* HPLCOM is high impedance when powered down, not fully powered up */
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aic3x_write_reg(AIC3X_HPLCOM_LVL, 0x04);
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}
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void audiohw_postinit(void)
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{
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audiohw_mute(false);
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audiohw_mute(false);
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/* Power up Left, Right DAC/LOP, HPLOUT and HPROUT */
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aic3x_write_reg(AIC3X_MOD_POWER, 0xFE);
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/* HPLOUT output level 0dB, not muted, fully powered up */
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aic3x_write_reg(AIC3X_HPLOUT_LVL, 0x09);
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/* HPROUT output level 0dB, not muted, fully powered up */
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aic3x_write_reg(AIC3X_HPROUT_LVL, 0x09);
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/* MONO_LOP output level 6dB, not muted */
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aic3x_write_reg(AIC3X_MONO_LOP_M_LVL, 0x69);
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/* PGA_R is not routed to MONO_LOP/M, analog gain -52.7dB */
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aic3x_write_reg(AIC3X_PGA_R_MONO_LOP_M_VOL, 0x69);
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}
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void audiohw_set_frequency(int fsel)
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@ -238,10 +291,46 @@ void audiohw_set_headphone_vol(int vol_l, int vol_r)
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/* Nice shutdown of AIC3X codec */
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void audiohw_close(void)
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{
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audiohw_mute(true);
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#ifdef SANSA_CONNECT
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avr_hid_reset_codec();
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#endif
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/* HPLOUT, HPROUT, HPLCOM not fully powered up */
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aic3x_change_reg(AIC3X_HPLOUT_LVL, 0x00, 0xFE);
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aic3x_change_reg(AIC3X_HPROUT_LVL, 0x00, 0xFE);
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aic3x_change_reg(AIC3X_HPLCOM_LVL, 0x00, 0xFC);
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/* MONO_LOP/M, LEFT_LOP/M, RIGHT_LOP/M muted, not fully powered up */
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aic3x_change_reg(AIC3X_MONO_LOP_M_LVL, 0x00, 0xF6);
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aic3x_change_reg(AIC3X_LEFT_LOP_M_LVL, 0x00, 0xF6);
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aic3x_change_reg(AIC3X_RIGHT_LOP_M_LVL, 0x00, 0xF6);
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/* Power down left and right DAC */
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aic3x_change_reg(AIC3X_DAC_POWER, 0x00, 0x30);
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/* Disable PLL */
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aic3x_change_reg(AIC3X_PLL_REG_A, 0x00, 0x7F);
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}
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void aic3x_switch_output(bool stereo)
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{
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if (stereo)
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{
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/* mute MONO_LOP/M */
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aic3x_change_reg(AIC3X_MONO_LOP_M_LVL, 0x00, 0xF6);
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/* HPLOUT fully powered up */
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aic3x_change_reg(AIC3X_HPLOUT_LVL, 0x01, 0xFF);
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/* HPROUT fully powered up */
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aic3x_change_reg(AIC3X_HPROUT_LVL, 0x01, 0xFF);
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/* HPLCOM fully powered up */
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aic3x_change_reg(AIC3X_HPLCOM_LVL, 0x01, 0xFF);
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}
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else
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{
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/* MONO_LOP/M not muted */
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aic3x_change_reg(AIC3X_MONO_LOP_M_LVL, 0x09, 0xFF);
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/* HPLOUT not fully powered up */
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aic3x_change_reg(AIC3X_HPLOUT_LVL, 0x00, 0xFE);
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/* HPROUT not fully powered up */
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aic3x_change_reg(AIC3X_HPROUT_LVL, 0x00, 0xFE);
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/* HPLCOM not fully powered up */
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aic3x_change_reg(AIC3X_HPLCOM_LVL, 0x00, 0xFE);
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}
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}
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@ -30,6 +30,8 @@ extern int tenthdb2master(int db);
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/*** definitions ***/
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extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
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extern void aic3x_switch_output(bool stereo);
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/* Page 0 registers */
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#define AIC3X_PAGE_SELECT 0
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#define AIC3X_SOFT_RESET 1
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@ -42,10 +44,17 @@ extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
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#define AIC3X_DATA_REG_A 8
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#define AIC3X_DATA_REG_B 9
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#define AIC3X_DATA_REG_C 10
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#define AIC3X_OVERFLOW 11
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#define AIC3X_LINE1L_LEFTADC 19
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#define AIC3X_LINE1R_RIGHTADC 22
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#define AIC3X_DAC_POWER 37
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#define AIC3X_HIGH_POWER 38
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#define AIC3X_POWER_OUT 40
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#define AIC3X_POP_REDUCT 42
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#define AIC3X_LEFT_VOL 43
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#define AIC3X_RIGHT_VOL 44
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@ -60,7 +69,9 @@ extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
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#define AIC3X_DAC_L1_MONO_LOP_M_VOL 75
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#define AIC3X_DAC_R1_MONO_LOP_M_VOL 76
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#define AIC3X_LINE2R_MONO_LOP_M_VOL 76
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#define AIC3X_PGA_R_MONO_LOP_M_VOL 77
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#define AIC3X_DAC_R1_MONO_LOP_M_VOL 78
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#define AIC3X_MONO_LOP_M_LVL 79
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@ -287,4 +287,10 @@ int i2c_read(unsigned short address, unsigned char* buf, int count)
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return i2c_read_data(dm320_i2c_bus, address, -1, buf, count);
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}
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int i2c_read_bytes(unsigned short address, unsigned short reg,
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unsigned char* buf, int count)
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{
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return i2c_read_data(dm320_i2c_bus, address, reg, buf, count);
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}
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#endif
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@ -19,6 +19,18 @@
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*
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****************************************************************************/
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#ifndef I2C_DM320_H
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#define I2C_DM320_H
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#include "system.h"
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void i2c_init(void);
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int i2c_write(unsigned short address, const unsigned char *data, int count);
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int i2c_read(unsigned short address, unsigned char* buf, int count);
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#ifdef HAVE_SOFTWARE_I2C
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int i2c_read_bytes(unsigned short address, unsigned short reg,
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unsigned char* buf, int count);
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#endif
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#endif
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@ -29,6 +29,7 @@
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#include "button.h"
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#include "backlight.h"
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#include "powermgmt.h"
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#include "aic3x.h"
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//#define BUTTON_DEBUG
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@ -405,6 +406,26 @@ void GIO0(void)
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/* interrupt will be enabled back after button read */
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queue_post(&btn_queue, BTN_INTERRUPT, 0);
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}
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void GIO2(void) __attribute__ ((section(".icode")));
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void GIO2(void)
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{
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/* Clear interrupt */
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IO_INTC_IRQ1 = (1 << 7);
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/* Disable interrupt */
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IO_INTC_EINT1 &= ~INTR_EINT1_EXT2;
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if (IO_GIO_BITSET0 & 0x04)
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{
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aic3x_switch_output(false);
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}
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else
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{
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aic3x_switch_output(true);
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}
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IO_INTC_EINT1 |= INTR_EINT1_EXT2;
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}
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#endif
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void button_init_device(void)
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|
|
@ -425,12 +446,13 @@ void button_init_device(void)
|
|||
avr_hid_get_state();
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
IO_GIO_IRQPORT |= 0x01; /* Enable GIO0 external interrupt */
|
||||
IO_GIO_INV0 &= ~0x01; /* Clear INV for GIO0 (falling edge detection) */
|
||||
IO_GIO_IRQEDGE &= ~0x01; /* Set edge detection (falling) */
|
||||
IO_GIO_IRQPORT |= 0x05; /* Enable GIO0/GIO2 external interrupt */
|
||||
IO_GIO_INV0 &= ~0x05; /* Clear INV for GIO0/GIO2 */
|
||||
/* falling edge detection on GIO0, any edge on GIO2 */
|
||||
IO_GIO_IRQEDGE = (IO_GIO_IRQEDGE & ~0x01) | 0x04;
|
||||
|
||||
/* Enable GIO0 interrupt */
|
||||
IO_INTC_EINT1 |= INTR_EINT1_EXT0;
|
||||
/* Enable GIO0 and GIO2 interrupts */
|
||||
IO_INTC_EINT1 |= INTR_EINT1_EXT0 | INTR_EINT1_EXT2;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,9 @@ static void tps65021_write_reg(unsigned reg, unsigned value)
|
|||
|
||||
void power_init(void)
|
||||
{
|
||||
/* Enable LDO */
|
||||
tps65021_write_reg(0x03, 0xFD);
|
||||
|
||||
/* PWM mode */
|
||||
tps65021_write_reg(0x04, 0xB2);
|
||||
|
||||
|
|
@ -61,6 +64,9 @@ void power_init(void)
|
|||
|
||||
void power_off(void)
|
||||
{
|
||||
/* Disable GIO0 and GIO2 interrupts */
|
||||
IO_INTC_EINT1 &= ~(INTR_EINT1_EXT2 | INTR_EINT1_EXT0);
|
||||
|
||||
avr_hid_reset_codec();
|
||||
avr_hid_power_off();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue