Sansav2 : initializes SDRAM
The AS3525 SoC ships with an ARM PL172 MPMC controller Also correct the memory sizes in tools/configure git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18899 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
a5a2f12f0a
commit
b3ee07c22e
4 changed files with 115 additions and 4 deletions
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@ -36,6 +36,8 @@ void main(void)
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int i;
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unsigned char buf[8];
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system_init();
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lcd_init_device();
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lcd_clear_display();
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@ -312,4 +312,39 @@ interface */
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#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
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#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a))))
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/* ARM PL172 Memory Controller registers */
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#define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000))
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#define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004))
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#define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008))
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#define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020))
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#define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024))
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#define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028))
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#define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030))
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#define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034))
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#define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038))
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#define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C))
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#define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040))
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#define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044))
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#define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048))
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#define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C))
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#define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050))
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#define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054))
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#define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058))
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#define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080))
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#define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100))
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#define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120))
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#define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140))
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#define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160))
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#define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104))
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#define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124))
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#define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144))
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#define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164))
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#define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8))
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#endif /*__AS3525_H__*/
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@ -8,6 +8,7 @@
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -124,10 +125,83 @@ void fiq_handler(void)
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);
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}
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static void sdram_delay(void)
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{
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int delay = 1024; /* arbitrary */
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while (delay--) ;
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}
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/* Use the same initialization than OF */
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static void sdram_init(void)
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{
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CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */
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CGU_PERI |= (1<<2); /* divider = 2 */
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CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */
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MPMC_CONTROL = 0x1; /* enable MPMC */
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MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
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MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
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if(MPMC_PERIPH_ID2 & 0xf0)
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MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
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/* timings */
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MPMC_DYNAMIC_tRP = 2;
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MPMC_DYNAMIC_tRAS = 4;
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MPMC_DYNAMIC_tSREX = 5;
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MPMC_DYNAMIC_tAPR = 0;
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MPMC_DYNAMIC_tDAL = 4;
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MPMC_DYNAMIC_tWR = 2;
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MPMC_DYNAMIC_tRC = 5;
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MPMC_DYNAMIC_tRFC = 5;
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MPMC_DYNAMIC_tXSR = 5;
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MPMC_DYNAMIC_tRRD = 2;
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MPMC_DYNAMIC_tMRD = 2;
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#if defined(SANSA_CLIP) || defined(SANSA_M200V2)
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# define MEMORY_MODEL 0x21
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/* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
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#elif defined(SANSA_E200V2)
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# define MEMORY_MODEL 0x5
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/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
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#else
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# error "The external memory in your player is unknown"
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#endif
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MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
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MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
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MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
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MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
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MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
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MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
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/* this part is required, if you know why please explain */
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unsigned int tmp = *(volatile unsigned int*)(0x30000000+0x2300*MEM);
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(void)tmp; /* we just need to read from this location */
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MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
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MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
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}
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void system_init(void)
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{
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/* CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; */
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#if 0 /* the GPIO clock is already enabled by the dualboot function */
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CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
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#endif
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sdram_init();
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}
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void system_reboot(void)
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6
tools/configure
vendored
6
tools/configure
vendored
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@ -1684,7 +1684,7 @@ fi
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target_id=50
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modelname="clip"
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target="-DSANSA_CLIP"
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memory=1 # In fact, 0.3125
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memory=2
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$bmp2rb_mono"
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@ -1704,7 +1704,7 @@ fi
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target_id=51
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modelname="e200v2"
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target="-DSANSA_E200V2"
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memory=2 # FIXME - a guess
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memory=8
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$bmp2rb_mono"
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@ -1724,7 +1724,7 @@ fi
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target_id=52
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modelname="m200v2"
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target="-DSANSA_M200V2"
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memory=2 # FIXME - A guess
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memory=2
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$bmp2rb_mono"
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