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iPod Nano 2G: Use sane (150 microseconds) PLL locking delays and properly set a third CLKCON register I just discovered

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28588 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann 2010-11-14 15:18:05 +00:00
parent 316986df67
commit b18d220e48
1 changed files with 6 additions and 2 deletions
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8
firmware/target/arm/s5l8700/crt0.S
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@ -136,9 +136,11 @@ start_loc:
ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0
#endif
str r0, [r1,#0x04] // PLL0PMS
ldr r0, =8100
mov r0, #0
str r0, [r1,#0x08] // PLL1PMS
ldr r0, =280
str r0, [r1,#0x14] // PLL0LCNT
mov r0, #1
mov r0, #3
str r0, [r1,#0x24] // PLLCON
1:
ldr r0, [r1,#0x20] // PLLLOCK
@ -148,6 +150,8 @@ start_loc:
str r0, [r1,#0x3c] // CLKCON2
ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
str r0, [r1] // CLKCON
mov r0, #0x37 // SCLK = 25MHz
str r0, [r1,#0x10] // CLKCON3
ldr r2, =0xc0000078
mrc 15, 0, r0, c1, c0, 0