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x1000: remove 'typedef struct' from NAND driver

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Using 'typedef struct' is not in line with the project coding style
and somewhat problematic, so get rid of it here.

Change-Id: Icfe79de72ed82cb7526e9f4e8296ec12084c01ac
This commit is contained in:
Aidan MacDonald 2022-06-07 18:06:31 +01:00
parent cc017f211a
commit ad8ace53e5
6 changed files with 47 additions and 47 deletions
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11
bootloader/x1000/utils.c
View file

@ -146,14 +146,15 @@ int load_uimage_file(const char* filename,
struct nand_reader_data
{
nand_drv* ndrv;
struct nand_drv* ndrv;
nand_page_t page;
nand_page_t end_page;
unsigned offset;
uint32_t count;
};
static int uimage_nand_reader_init(struct nand_reader_data* d, nand_drv* ndrv,
static int uimage_nand_reader_init(struct nand_reader_data* d,
struct nand_drv* ndrv,
uint32_t addr, uint32_t length)
{
unsigned pg_size = ndrv->chip->page_size;
@ -177,7 +178,7 @@ static int uimage_nand_reader_init(struct nand_reader_data* d, nand_drv* ndrv,
static ssize_t uimage_nand_reader(void* buf, size_t count, void* rctx)
{
struct nand_reader_data* d = rctx;
nand_drv* ndrv = d->ndrv;
struct nand_drv* ndrv = d->ndrv;
unsigned pg_size = ndrv->chip->page_size;
size_t read_count = 0;
int rc;
@ -223,7 +224,7 @@ static ssize_t uimage_nand_reader(void* buf, size_t count, void* rctx)
int load_uimage_flash(uint32_t addr, uint32_t length,
struct uimage_header* uh, size_t* sizep)
{
nand_drv* ndrv = nand_init();
struct nand_drv* ndrv = nand_init();
nand_lock(ndrv);
if(nand_open(ndrv) != NAND_SUCCESS) {
splashf(5*HZ, "NAND open failed");
@ -259,7 +260,7 @@ int dump_flash(int fd, uint32_t addr, uint32_t length)
static char buf[8192];
int ret = 0;
nand_drv* ndrv = nand_init();
struct nand_drv* ndrv = nand_init();
nand_lock(ndrv);
ret = nand_open(ndrv);

2
firmware/target/mips/ingenic_x1000/boot-x1000.c
View file

@ -267,7 +267,7 @@ void x1000_dualboot_init_uart2(void)
int x1000_dualboot_load_pdma_fw(void)
{
nand_drv* n = nand_init();
struct nand_drv* n = nand_init();
nand_lock(n);
int ret = nand_open(n);

4
firmware/target/mips/ingenic_x1000/installer-x1000.c
View file

@ -65,7 +65,7 @@ static const int num_updates = sizeof(updates) / sizeof(struct update_part);
/* calculate the offset and length of the update image; this is constant
* for a given target, based on the update parts and the NAND chip geometry.
*/
static void get_image_loc(nand_drv* ndrv, size_t* offptr, size_t* lenptr)
static void get_image_loc(struct nand_drv* ndrv, size_t* offptr, size_t* lenptr)
{
size_t blk_size = ndrv->chip->page_size << ndrv->chip->log2_ppb;
size_t img_off = 0;
@ -119,7 +119,7 @@ struct updater {
size_t img_len; /* image length in flash = size of the buffer */
mtar_t* tar;
nand_drv* ndrv;
struct nand_drv* ndrv;
};
static int updater_init(struct updater* u)

41
firmware/target/mips/ingenic_x1000/nand-x1000.c
View file

@ -24,7 +24,7 @@
#include "system.h"
#include <string.h>
const nand_chip supported_nand_chips[] = {
const struct nand_chip supported_nand_chips[] = {
#if defined(FIIO_M3K) || defined(SHANLING_Q1) || defined(EROS_QN)
{
/* ATO25D1GA */
@ -51,14 +51,13 @@ const nand_chip supported_nand_chips[] = {
#endif
};
const size_t nr_supported_nand_chips =
sizeof(supported_nand_chips) / sizeof(nand_chip);
const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips);
static nand_drv static_nand_drv;
static struct nand_drv static_nand_drv;
static uint8_t static_scratch_buf[NAND_DRV_SCRATCHSIZE] CACHEALIGN_ATTR;
static uint8_t static_page_buf[NAND_DRV_MAXPAGESIZE] CACHEALIGN_ATTR;
nand_drv* nand_init(void)
struct nand_drv* nand_init(void)
{
static bool inited = false;
if(!inited) {
@ -71,19 +70,19 @@ nand_drv* nand_init(void)
return &static_nand_drv;
}
static uint8_t nand_get_reg(nand_drv* drv, uint8_t reg)
static uint8_t nand_get_reg(struct nand_drv* drv, uint8_t reg)
{
sfc_exec(NANDCMD_GET_FEATURE, reg, drv->scratch_buf, 1|SFC_READ);
return drv->scratch_buf[0];
}
static void nand_set_reg(nand_drv* drv, uint8_t reg, uint8_t val)
static void nand_set_reg(struct nand_drv* drv, uint8_t reg, uint8_t val)
{
drv->scratch_buf[0] = val;
sfc_exec(NANDCMD_SET_FEATURE, reg, drv->scratch_buf, 1|SFC_WRITE);
}
static void nand_upd_reg(nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val)
static void nand_upd_reg(struct nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val)
{
uint8_t x = nand_get_reg(drv, reg);
x &= ~msk;
@ -91,7 +90,7 @@ static void nand_upd_reg(nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val)
nand_set_reg(drv, reg, x);
}
static bool identify_chip(nand_drv* drv)
static bool identify_chip(struct nand_drv* drv)
{
/* Read ID command has some variations; Linux handles these 3:
* - no address or dummy bytes
@ -106,7 +105,7 @@ static bool identify_chip(nand_drv* drv)
drv->dev_id2 = drv->scratch_buf[2];
for(size_t i = 0; i < nr_supported_nand_chips; ++i) {
const nand_chip* chip = &supported_nand_chips[i];
const struct nand_chip* chip = &supported_nand_chips[i];
if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id)
continue;
@ -121,13 +120,13 @@ static bool identify_chip(nand_drv* drv)
return false;
}
static void setup_chip_data(nand_drv* drv)
static void setup_chip_data(struct nand_drv* drv)
{
drv->ppb = 1 << drv->chip->log2_ppb;
drv->fpage_size = drv->chip->page_size + drv->chip->oob_size;
}
static void setup_chip_commands(nand_drv* drv)
static void setup_chip_commands(struct nand_drv* drv)
{
/* Select commands appropriate for the chip */
drv->cmd_page_read = NANDCMD_PAGE_READ(drv->chip->row_cycles);
@ -143,7 +142,7 @@ static void setup_chip_commands(nand_drv* drv)
}
}
static void setup_chip_registers(nand_drv* drv)
static void setup_chip_registers(struct nand_drv* drv)
{
/* Set chip registers to enter normal operation */
if(drv->chip->flags & NAND_CHIPFLAG_HAS_QE_BIT) {
@ -159,7 +158,7 @@ static void setup_chip_registers(nand_drv* drv)
nand_set_reg(drv, FREG_PROT, FREG_PROT_UNLOCK);
}
int nand_open(nand_drv* drv)
int nand_open(struct nand_drv* drv)
{
if(drv->refcount > 0) {
drv->refcount++;
@ -193,7 +192,7 @@ int nand_open(nand_drv* drv)
return NAND_SUCCESS;
}
void nand_close(nand_drv* drv)
void nand_close(struct nand_drv* drv)
{
--drv->refcount;
if(drv->refcount > 0)
@ -207,7 +206,7 @@ void nand_close(nand_drv* drv)
sfc_close();
}
static uint8_t nand_wait_busy(nand_drv* drv)
static uint8_t nand_wait_busy(struct nand_drv* drv)
{
uint8_t reg;
do {
@ -216,7 +215,7 @@ static uint8_t nand_wait_busy(nand_drv* drv)
return reg;
}
int nand_block_erase(nand_drv* drv, nand_block_t block)
int nand_block_erase(struct nand_drv* drv, nand_block_t block)
{
sfc_exec(NANDCMD_WR_EN, 0, NULL, 0);
sfc_exec(drv->cmd_block_erase, block, NULL, 0);
@ -228,7 +227,7 @@ int nand_block_erase(nand_drv* drv, nand_block_t block)
return NAND_SUCCESS;
}
int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer)
int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer)
{
sfc_exec(NANDCMD_WR_EN, 0, NULL, 0);
sfc_exec(drv->cmd_program_load, 0, (void*)buffer, drv->fpage_size|SFC_WRITE);
@ -241,7 +240,7 @@ int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer)
return NAND_SUCCESS;
}
int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer)
int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer)
{
sfc_exec(drv->cmd_page_read, page, NULL, 0);
nand_wait_busy(drv);
@ -249,7 +248,7 @@ int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer)
return NAND_SUCCESS;
}
int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer)
int nand_read_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer)
{
if(byte_len == 0)
return NAND_SUCCESS;
@ -277,7 +276,7 @@ int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void*
return NAND_SUCCESS;
}
int nand_write_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer)
int nand_write_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer)
{
if(byte_len == 0)
return NAND_SUCCESS;

32
firmware/target/mips/ingenic_x1000/nand-x1000.h
View file

@ -95,7 +95,7 @@
typedef uint32_t nand_block_t;
typedef uint32_t nand_page_t;
typedef struct nand_chip {
struct nand_chip {
/* Manufacturer and device ID bytes */
uint8_t mf_id;
uint8_t dev_id;
@ -126,9 +126,9 @@ typedef struct nand_chip {
/* Chip specific flags */
uint32_t flags;
} nand_chip;
};
typedef struct nand_drv {
struct nand_drv {
/* NAND access lock. Needs to be held during any operations. */
struct mutex mutex;
@ -150,7 +150,7 @@ typedef struct nand_drv {
uint8_t* page_buf;
/* Pointer to the chip data. */
const nand_chip* chip;
const struct nand_chip* chip;
/* Pages per block = 1 << chip->log2_ppb */
unsigned ppb;
@ -169,9 +169,9 @@ typedef struct nand_drv {
uint32_t cmd_program_load;
uint32_t cmd_program_execute;
uint32_t cmd_block_erase;
} nand_drv;
};
extern const nand_chip supported_nand_chips[];
extern const struct nand_chip supported_nand_chips[];
extern const size_t nr_supported_nand_chips;
/* Return the static NAND driver instance.
@ -179,14 +179,14 @@ extern const size_t nr_supported_nand_chips;
* ALL normal Rockbox code should use this instance. The SPL does not
* use it, because it needs to manually place buffers in external RAM.
*/
extern nand_drv* nand_init(void);
extern struct nand_drv* nand_init(void);
static inline void nand_lock(nand_drv* drv)
static inline void nand_lock(struct nand_drv* drv)
{
mutex_lock(&drv->mutex);
}
static inline void nand_unlock(nand_drv* drv)
static inline void nand_unlock(struct nand_drv* drv)
{
mutex_unlock(&drv->mutex);
}
@ -200,8 +200,8 @@ static inline void nand_unlock(nand_drv* drv)
*
* These functions require the lock to be held.
*/
extern int nand_open(nand_drv* drv);
extern void nand_close(nand_drv* drv);
extern int nand_open(struct nand_drv* drv);
extern void nand_close(struct nand_drv* drv);
/* Read / program / erase operations. Buffer needs to be cache-aligned for DMA.
* Read and program operate on full page data, ie. including OOB data areas.
@ -209,15 +209,15 @@ extern void nand_close(nand_drv* drv);
* NOTE: ECC is not implemented. If it ever needs to be, these functions will
* probably use ECC transparently. All code should be written to expect this.
*/
extern int nand_block_erase(nand_drv* drv, nand_block_t block);
extern int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer);
extern int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer);
extern int nand_block_erase(struct nand_drv* drv, nand_block_t block);
extern int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer);
extern int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer);
/* Wrappers to read/write bytes. For simple access to the main data area only.
* The write address / length must align to a block boundary. Reads do not have
* any alignment requirement. OOB data is never read, and is written as 0xff.
*/
extern int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer);
extern int nand_write_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer);
extern int nand_read_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer);
extern int nand_write_bytes(struct nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer);
#endif /* __NAND_X1000_H__ */

4
firmware/target/mips/ingenic_x1000/spl-nand-x1000.c
View file

@ -23,7 +23,7 @@
#include "gpio-x1000.h"
#include "nand-x1000.h"
static nand_drv* ndrv = NULL;
static struct nand_drv* ndrv = NULL;
int spl_storage_open(void)
{
@ -31,7 +31,7 @@ int spl_storage_open(void)
gpioz_configure(GPIO_A, 0x3f << 26, GPIOF_DEVICE(1));
/* Allocate NAND driver manually in DRAM */
ndrv = spl_alloc(sizeof(nand_drv));
ndrv = spl_alloc(sizeof(struct nand_drv));
ndrv->page_buf = spl_alloc(NAND_DRV_MAXPAGESIZE);
ndrv->scratch_buf = spl_alloc(NAND_DRV_SCRATCHSIZE);
ndrv->refcount = 0;