Read/write Nano2G FTL/NAND driver by Michael Sparmann (FS#10633).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22918 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman
parent
61dc1c507c
commit
a7ea270e9c
7 changed files with 2288 additions and 9 deletions
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@ -1330,6 +1330,8 @@ target/arm/s5l8700/ipodnano2g/lcd-nano2g.c
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target/arm/s5l8700/ipodnano2g/powermgmt-nano2g.c
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target/arm/s5l8700/ipodnano2g/power-nano2g.c
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target/arm/s5l8700/ipodnano2g/audio-nano2g.c
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target/arm/s5l8700/ipodnano2g/ftl-nano2g.c
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target/arm/s5l8700/ipodnano2g/nand-nano2g.c
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#endif
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#ifndef SIMULATOR
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@ -58,6 +58,9 @@
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#define CONFIG_NAND NAND_SAMSUNG
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/* The NAND flash has 2048-byte sectors, and is our only storage */
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#define SECTOR_SIZE 2048
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/* LCD dimensions */
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#define LCD_WIDTH 176
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#define LCD_HEIGHT 132
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@ -18,15 +18,17 @@
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "nand.h"
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#include "config.h"
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#include "ata_idle_notify.h"
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#include "system.h"
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#include <string.h>
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#include "thread.h"
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#include "led.h"
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#include "disk.h"
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#include "storage.h"
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#include "panic.h"
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#include "usb.h"
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#include "ftl-target.h"
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/* for compatibility */
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long last_disk_activity = -1;
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@ -47,19 +49,13 @@ void nand_led(bool onoff)
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int nand_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
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void* inbuf)
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{
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(void)start;
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(void)incount;
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(void)inbuf;
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return 0;
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return ftl_read(start, incount, inbuf);
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}
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int nand_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
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const void* outbuf)
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{
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(void)start;
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(void)count;
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(void)outbuf;
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return 0;
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return ftl_write(start, count, outbuf);
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}
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void nand_spindown(int seconds)
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@ -92,6 +88,8 @@ long nand_last_disk_activity(void)
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int nand_init(void)
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{
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if (ftl_init()) return 1;
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initialized = true;
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return 0;
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}
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1789
firmware/target/arm/s5l8700/ipodnano2g/ftl-nano2g.c
Normal file
1789
firmware/target/arm/s5l8700/ipodnano2g/ftl-nano2g.c
Normal file
File diff suppressed because it is too large
Load diff
34
firmware/target/arm/s5l8700/ipodnano2g/ftl-target.h
Normal file
34
firmware/target/arm/s5l8700/ipodnano2g/ftl-target.h
Normal file
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@ -0,0 +1,34 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __FTL_H__
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#define __FTL_H__
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#include "config.h"
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#include "inttypes.h"
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uint32_t ftl_init(void);
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uint32_t ftl_read(uint32_t sector, uint32_t count, void* buffer);
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uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer);
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uint32_t ftl_sync(void);
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#endif
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399
firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
Normal file
399
firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
Normal file
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@ -0,0 +1,399 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "cpu.h"
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#include "inttypes.h"
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#include "nand-target.h"
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#include <string.h>
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#define NAND_CMD_READ 0x00
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#define NAND_CMD_PROGCNFRM 0x10
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#define NAND_CMD_READ2 0x30
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#define NAND_CMD_BLOCKERASE 0x60
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#define NAND_CMD_GET_STATUS 0x70
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#define NAND_CMD_PROGRAM 0x80
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#define NAND_CMD_ERASECNFRM 0xD0
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#define NAND_CMD_RESET 0xFF
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#define NAND_STATUS_READY 0x40
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#define NAND_DEVICEINFOTABLE_ENTRIES 33
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static const struct nand_device_info_type nand_deviceinfotable[] =
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{
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{0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
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{0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
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{0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
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{0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
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{0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
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{0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
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{0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
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{0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
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{0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
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{0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
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{0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
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{0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
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{0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
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{0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
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{0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
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{0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
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};
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uint8_t nand_tunk1[4];
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uint8_t nand_twp[4];
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uint8_t nand_tunk2[4];
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uint8_t nand_tunk3[4];
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uint32_t nand_type[4];
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static uint8_t nand_aligned_data[0x800] __attribute__((aligned(32)));
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static uint8_t nand_aligned_ctrl[0x200] __attribute__((aligned(32)));
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static uint8_t nand_aligned_spare[0x40] __attribute__((aligned(32)));
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static uint8_t nand_aligned_ecc[0x28] __attribute__((aligned(32)));
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#define nand_uncached_data \
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((uint8_t*)(((uint32_t)nand_aligned_data) | 0x40000000))
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#define nand_uncached_ctrl \
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((uint8_t*)(((uint32_t)nand_aligned_ctrl) | 0x40000000))
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#define nand_uncached_spare \
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((uint8_t*)(((uint32_t)nand_aligned_spare) | 0x40000000))
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#define nand_uncached_ecc \
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((uint8_t*)(((uint32_t)nand_aligned_ecc) | 0x40000000))
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uint32_t nand_wait_rbbdone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_RBBDONE) == 0) if (timeout-- == 0) return 1;
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FMCSTAT = FMCSTAT_RBBDONE;
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return 0;
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}
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uint32_t nand_wait_cmddone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_CMDDONE) == 0) if (timeout-- == 0) return 1;
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FMCSTAT = FMCSTAT_CMDDONE;
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return 0;
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}
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uint32_t nand_wait_addrdone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_ADDRDONE) == 0) if (timeout-- == 0) return 1;
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FMCSTAT = FMCSTAT_ADDRDONE;
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return 0;
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}
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uint32_t nand_wait_chip_ready(uint32_t bank)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & (FMCSTAT_BANK0READY << bank)) == 0)
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if (timeout-- == 0) return 1;
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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return 0;
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}
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void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
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{
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FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
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| (1 << 11) | 1 | (1 << (bank + 1)) | flags;
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}
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uint32_t nand_send_cmd(uint32_t cmd)
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{
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FMCMD = cmd;
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return nand_wait_rbbdone();
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}
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uint32_t nand_send_address(uint32_t page, uint32_t offset)
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{
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FMANUM = 4;
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FMADDR0 = (page << 16) | offset;
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FMADDR1 = (page >> 16) & 0xFF;
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FMCTRL1 = FMCTRL1_DOTRANSADDR;
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return nand_wait_cmddone();
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}
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uint32_t nand_reset(uint32_t bank)
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{
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nand_set_fmctrl0(bank, 0);
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if (nand_send_cmd(NAND_CMD_RESET) != 0) return 1;
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if (nand_wait_chip_ready(bank) != 0) return 1;
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return 0;
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}
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uint32_t nand_wait_status_ready(uint32_t bank)
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{
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uint32_t timeout = 0x4000;
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nand_set_fmctrl0(bank, 0);
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if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)) != 0)
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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if (nand_send_cmd(NAND_CMD_GET_STATUS) != 0) return 1;
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while (1)
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{
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if (timeout-- == 0) return 1;
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FMDNUM = 0;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone() != 0) return 1;
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if ((FMFIFO & NAND_STATUS_READY) != 0) break;
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FMCTRL1 = FMCTRL1_CLEARRFIFO;
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}
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FMCTRL1 = FMCTRL1_CLEARRFIFO;
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return nand_send_cmd(NAND_CMD_READ);
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}
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uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
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void* buffer, uint32_t size)
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{
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uint32_t timeout = 0x40000;
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nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
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FMDNUM = size - 1;
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FMCTRL1 = FMCTRL1_DOREADDATA << direction;
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DMACON3 = (2 << DMACON_DEVICE_SHIFT)
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| (direction << DMACON_DIRECTION_SHIFT)
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| (2 << DMACON_DATA_SIZE_SHIFT)
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| (3 << DMACON_BURST_LEN_SHIFT);
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while ((DMAALLST & DMAALLST_CHAN3_MASK) != 0)
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DMACOM3 = DMACOM_CLEARBOTHDONE;
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DMABASE3 = (uint32_t)buffer;
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DMATCNT3 = (size >> 4) - 1;
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DMACOM3 = 4;
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while ((DMAALLST & DMAALLST_DMABUSY3) != 0)
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if (timeout-- == 0) return 1;
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if (nand_wait_addrdone() != 0) return 1;
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if (direction == 0) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return 0;
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}
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uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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uint32_t timeout = 0x40000;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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ECC_CTRL = ECCCTRL_STARTDECODING;
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while ((SRCPND & INTMSK_ECC) == 0) if (timeout-- == 0) return 1;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return ECC_RESULT;
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}
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uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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uint32_t timeout = 0x40000;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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ECC_CTRL = ECCCTRL_STARTENCODING;
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while ((SRCPND & INTMSK_ECC) == 0) if (timeout-- == 0) return 1;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return 0;
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}
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uint32_t nand_check_empty(uint8_t* buffer)
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{
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uint32_t i, count;
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count = 0;
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for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
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if (count < 2) return 1;
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return 0;
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}
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uint32_t nand_get_chip_type(uint32_t bank)
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{
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uint32_t result;
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if (nand_reset(bank) != 0) return 0xFFFFFFFF;
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if (nand_send_cmd(0x90) != 0) return 0xFFFFFFFF;
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FMANUM = 0;
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FMADDR0 = 0;
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FMCTRL1 = FMCTRL1_DOTRANSADDR;
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if (nand_wait_cmddone() != 0) return 0xFFFFFFFF;
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FMDNUM = 4;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone() != 0) return 0xFFFFFFFF;
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result = FMFIFO;
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return result;
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}
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uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc,
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uint32_t checkempty)
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{
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uint32_t rc, eccresult;
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nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
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if (nand_send_cmd(NAND_CMD_READ) != 0) return 1;
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if (nand_send_address(page, (databuffer == 0) ? 0x800 : 0) != 0)
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return 1;
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if (nand_send_cmd(NAND_CMD_READ2) != 0) return 1;
|
||||
if (nand_wait_status_ready(bank) != 0) return 1;
|
||||
if (databuffer != 0)
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_data, 0x800) != 0)
|
||||
return 1;
|
||||
if (doecc == 0)
|
||||
{
|
||||
memcpy(databuffer, nand_uncached_data, 0x800);
|
||||
if (sparebuffer != 0)
|
||||
{
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
memcpy(sparebuffer, nand_uncached_spare, 0x800);
|
||||
if (checkempty != 0)
|
||||
return nand_check_empty((uint8_t*)sparebuffer) << 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
rc = 0;
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
memcpy(nand_uncached_ecc, &nand_uncached_spare[0xC], 0x28);
|
||||
rc |= (ecc_decode(3, nand_uncached_data, nand_uncached_ecc) & 0xF) << 4;
|
||||
if (databuffer != 0) memcpy(databuffer, nand_uncached_data, 0x800);
|
||||
memset(nand_uncached_ctrl, 0xFF, 0x200);
|
||||
memcpy(nand_uncached_ctrl, nand_uncached_spare, 0xC);
|
||||
memcpy(nand_uncached_ecc, &nand_uncached_spare[0x34], 0xC);
|
||||
eccresult = ecc_decode(0, nand_uncached_ctrl, nand_uncached_ecc);
|
||||
rc |= (eccresult & 0xF) << 8;
|
||||
if (sparebuffer != 0)
|
||||
{
|
||||
memcpy(sparebuffer, nand_uncached_spare, 0x40);
|
||||
if ((eccresult & 1) != 0) memset(sparebuffer, 0xFF, 0xC);
|
||||
else memcpy(sparebuffer, nand_uncached_ctrl, 0xC);
|
||||
}
|
||||
if (checkempty != 0) rc |= nand_check_empty(nand_uncached_spare) << 1;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||
void* sparebuffer, uint32_t doecc)
|
||||
{
|
||||
if (sparebuffer != 0) memcpy(nand_uncached_spare, sparebuffer, 0x40);
|
||||
else memset(nand_uncached_spare, 0xFF, 0x40);
|
||||
if (doecc != 0)
|
||||
{
|
||||
memcpy(nand_uncached_data, databuffer, 0x800);
|
||||
if (ecc_encode(3, nand_uncached_data, nand_uncached_ecc) != 0)
|
||||
return 1;
|
||||
memcpy(&nand_uncached_spare[0xC], nand_uncached_ecc, 0x28);
|
||||
memset(nand_uncached_ctrl, 0xFF, 0x200);
|
||||
memcpy(nand_uncached_ctrl, nand_uncached_spare, 0xC);
|
||||
if (ecc_encode(0, nand_uncached_ctrl, nand_uncached_ecc) != 0)
|
||||
return 1;
|
||||
memcpy(&nand_uncached_spare[0x34], nand_uncached_ecc, 0xC);
|
||||
}
|
||||
nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
|
||||
if (nand_send_cmd(NAND_CMD_PROGRAM) != 0)
|
||||
return 1;
|
||||
if (nand_send_address(page, (databuffer == 0) ? 0x800 : 0) != 0)
|
||||
return 1;
|
||||
if (databuffer != 0)
|
||||
if (nand_transfer_data(bank, 1, nand_uncached_data, 0x800) != 0)
|
||||
return 1;
|
||||
if (sparebuffer != 0 || doecc != 0)
|
||||
if (nand_transfer_data(bank, 1, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
if (nand_send_cmd(NAND_CMD_PROGCNFRM) != 0) return 1;
|
||||
return nand_wait_status_ready(bank);
|
||||
}
|
||||
|
||||
uint32_t nand_block_erase(uint32_t bank, uint32_t page)
|
||||
{
|
||||
nand_set_fmctrl0(bank, 0);
|
||||
if (nand_send_cmd(NAND_CMD_BLOCKERASE) != 0) return 1;
|
||||
FMANUM = 2;
|
||||
FMADDR0 = page;
|
||||
FMCTRL1 = FMCTRL1_DOTRANSADDR;
|
||||
if (nand_wait_cmddone() != 0) return 1;
|
||||
if (nand_send_cmd(NAND_CMD_ERASECNFRM) != 0) return 1;
|
||||
return nand_wait_status_ready(bank);
|
||||
}
|
||||
|
||||
const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
|
||||
{
|
||||
if (nand_type[bank] == 0xFFFFFFFF)
|
||||
return (struct nand_device_info_type*)0;
|
||||
return &nand_deviceinfotable[nand_type[bank]];
|
||||
}
|
||||
|
||||
uint32_t nand_device_init(void)
|
||||
{
|
||||
uint32_t type;
|
||||
uint32_t i, j;
|
||||
PCON2 = 0x33333333;
|
||||
PDAT2 = 0;
|
||||
PCON3 = 0x11113333;
|
||||
PDAT3 = 0;
|
||||
PCON4 = 0x33333333;
|
||||
PDAT4 = 0;
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
nand_tunk1[i] = 7;
|
||||
nand_twp[i] = 7;
|
||||
nand_tunk2[i] = 7;
|
||||
nand_tunk3[i] = 7;
|
||||
type = nand_get_chip_type(i);
|
||||
nand_type[i] = 0xFFFFFFFF;
|
||||
if (type == 0xFFFFFFFF) continue;
|
||||
for (j = 0; ; j++)
|
||||
{
|
||||
if (j == ARRAYLEN(nand_deviceinfotable)) break;
|
||||
else if (nand_deviceinfotable[j].id == type)
|
||||
{
|
||||
nand_type[i] = j;
|
||||
break;
|
||||
}
|
||||
}
|
||||
nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
|
||||
nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
|
||||
nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
|
||||
nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
|
||||
}
|
||||
if (nand_type[0] == 0xFFFFFFFF) return 1;
|
||||
return 0;
|
||||
}
|
||||
54
firmware/target/arm/s5l8700/ipodnano2g/nand-target.h
Normal file
54
firmware/target/arm/s5l8700/ipodnano2g/nand-target.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2009 by Michael Sparmann
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __NAND_H__
|
||||
#define __NAND_H__
|
||||
|
||||
#include "config.h"
|
||||
#include "inttypes.h"
|
||||
|
||||
|
||||
struct nand_device_info_type
|
||||
{
|
||||
uint32_t id;
|
||||
uint16_t blocks;
|
||||
uint32_t userblocks;
|
||||
uint16_t pagesperblock;
|
||||
uint8_t blocksizeexponent;
|
||||
uint8_t tunk1;
|
||||
uint8_t twp;
|
||||
uint8_t tunk2;
|
||||
uint8_t tunk3;
|
||||
} __attribute__((packed));
|
||||
|
||||
uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||
void* sparebuffer, uint32_t doecc,
|
||||
uint32_t checkempty);
|
||||
uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||
void* sparebuffer, uint32_t doecc);
|
||||
uint32_t nand_block_erase(uint32_t bank, uint32_t page);
|
||||
|
||||
const struct nand_device_info_type* nand_get_device_type(uint32_t bank);
|
||||
uint32_t nand_reset(uint32_t bank);
|
||||
uint32_t nand_device_init(void);
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue