Apply FS#9650 (by Thomas Martitz). This adds hotswap and microSD support for the Fuze. It doesn't seem to work for all cards yet.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19447 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Frank Gevaerts
parent
1388bd3430
commit
9f37f04619
2 changed files with 105 additions and 18 deletions
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@ -306,20 +306,48 @@ interface */
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/* GPIO registers */
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#define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400))
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#define GPIOA_IS (*(volatile unsigned char*)(GPIOA_BASE+0x404))
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#define GPIOA_IBE (*(volatile unsigned char*)(GPIOA_BASE+0x408))
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#define GPIOA_IEV (*(volatile unsigned char*)(GPIOA_BASE+0x40C))
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#define GPIOA_IE (*(volatile unsigned char*)(GPIOA_BASE+0x410))
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#define GPIOA_RIS (*(volatile unsigned char*)(GPIOA_BASE+0x414))
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#define GPIOA_MIS (*(volatile unsigned char*)(GPIOA_BASE+0x418))
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#define GPIOA_IC (*(volatile unsigned char*)(GPIOA_BASE+0x41C))
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#define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420))
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#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+4*(1<<(a))))
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#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2))))
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#define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400))
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#define GPIOB_IS (*(volatile unsigned char*)(GPIOB_BASE+0x404))
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#define GPIOB_IBE (*(volatile unsigned char*)(GPIOB_BASE+0x408))
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#define GPIOB_IEV (*(volatile unsigned char*)(GPIOB_BASE+0x40C))
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#define GPIOB_IE (*(volatile unsigned char*)(GPIOB_BASE+0x410))
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#define GPIOB_RIS (*(volatile unsigned char*)(GPIOB_BASE+0x414))
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#define GPIOB_MIS (*(volatile unsigned char*)(GPIOB_BASE+0x418))
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#define GPIOB_IC (*(volatile unsigned char*)(GPIOB_BASE+0x41C))
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#define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420))
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#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+4*(1<<(a))))
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#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2))))
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#define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400))
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#define GPIOC_IS (*(volatile unsigned char*)(GPIOC_BASE+0x404))
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#define GPIOC_IBE (*(volatile unsigned char*)(GPIOC_BASE+0x408))
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#define GPIOC_IEV (*(volatile unsigned char*)(GPIOC_BASE+0x40C))
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#define GPIOC_IE (*(volatile unsigned char*)(GPIOC_BASE+0x410))
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#define GPIOC_RIS (*(volatile unsigned char*)(GPIOC_BASE+0x414))
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#define GPIOC_MIS (*(volatile unsigned char*)(GPIOC_BASE+0x418))
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#define GPIOC_IC (*(volatile unsigned char*)(GPIOC_BASE+0x41C))
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#define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420))
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#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+4*(1<<(a))))
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#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2))))
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#define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400))
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#define GPIOD_IS (*(volatile unsigned char*)(GPIOD_BASE+0x404))
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#define GPIOD_IBE (*(volatile unsigned char*)(GPIOD_BASE+0x408))
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#define GPIOD_IEV (*(volatile unsigned char*)(GPIOD_BASE+0x40C))
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#define GPIOD_IE (*(volatile unsigned char*)(GPIOD_BASE+0x410))
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#define GPIOD_RIS (*(volatile unsigned char*)(GPIOD_BASE+0x414))
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#define GPIOD_MIS (*(volatile unsigned char*)(GPIOD_BASE+0x418))
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#define GPIOD_IC (*(volatile unsigned char*)(GPIOD_BASE+0x41C))
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#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
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#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a))))
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#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2))))
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/* ARM PL172 Memory Controller registers */
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@ -84,6 +84,8 @@ static const int pl180_base[NUM_VOLUMES] = {
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#endif
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};
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static int sd_init_card(const int drive);
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static void init_pl180_controller(const int drive);
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/* TODO : BLOCK_SIZE != SECTOR_SIZE ? */
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#define BLOCK_SIZE 512
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#define SECTOR_SIZE 512
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@ -100,6 +102,7 @@ static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
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static const char sd_thread_name[] = "ata/sd";
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static struct mutex sd_mtx SHAREDBSS_ATTR;
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static struct event_queue sd_queue;
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static bool sd_enabled = false;
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static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
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@ -148,6 +151,33 @@ static void sd_panic(IF_MV2(const int drive,) const int status)
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(status & MCI_TX_FIFO_EMPTY) ? "TX FIFO EMPTY" : "");
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}
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#ifdef HAVE_HOTSWAP
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#ifdef SANSA_FUZE
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static bool sd1_oneshot_callback(struct timeout *tmo)
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{
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(void)tmo;
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/* This is called only if the state was stable for 300ms - check state
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* and post appropriate event. */
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if (card_detect_target())
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{
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queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
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}
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else
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queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
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return false;
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}
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void INT_GPIOA(void)
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{
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static struct timeout sd1_oneshot;
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/* reset irq */
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GPIOA_IC = (1<<2);
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timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
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}
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#endif
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#endif
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void INT_NAND(void)
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{
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sd_panic(IF_MV2(INTERNAL_AS3525,) MCI_STATUS(INTERNAL_AS3525));
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@ -348,7 +378,13 @@ static void sd_thread(void)
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card_info[1].initialized = 0;
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if (ev.id == SYS_HOTSWAP_INSERTED)
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{
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disk_mount(1);
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}
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else
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{
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init_pl180_controller(SD_SLOT_AS3525);
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}
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queue_broadcast(SYS_FS_CHANGED, 0);
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@ -399,6 +435,18 @@ static void init_pl180_controller(const int drive)
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#ifdef HAVE_MULTIVOLUME
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VIC_INT_ENABLE |=
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(drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
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#ifdef SANSA_FUZE
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/* setup isr for microsd monitoring */
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VIC_INT_ENABLE |= (INTERRUPT_GPIOA);
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/* clear previous irq */
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GPIOA_IC |= (1<<2);
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/* enable edge detecting */
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GPIOA_IS &= ~(1<<2);
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/* detect both raising and falling edges */
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GPIOA_IBE |= (1<<2);
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#endif
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#else
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VIC_INT_ENABLE |= INTERRUPT_NAND;
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#endif
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@ -496,7 +544,6 @@ static int sd_wait_for_state(const int drive, unsigned int state)
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{
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unsigned int response = 0;
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unsigned int timeout = 100; /* ticks */
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long t = current_tick;
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while (1)
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@ -528,7 +575,7 @@ static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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#ifndef HAVE_MULTIVOLUME
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const int drive = 0;
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#endif
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int ret;
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int ret = 0;
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/* skip SanDisk OF */
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if (drive == INTERNAL_AS3525)
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@ -552,19 +599,21 @@ static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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}
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#endif
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if (card_info[drive].initialized < 0)
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if (card_info[drive].initialized <= 0)
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{
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ret = card_info[drive].initialized;
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panicf("card not initialised");
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goto sd_transfer_error;
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sd_init_card(drive);
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if (!(card_info[drive].initialized))
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{
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panicf("card not initialised");
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goto sd_transfer_error;
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}
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}
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last_disk_activity = current_tick;
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ret = sd_wait_for_state(drive, SD_TRAN);
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if (ret < 0)
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{
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panicf("wait for state failed");
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panicf("wait for state failed on drive %d", drive);
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goto sd_transfer_error;
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}
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@ -689,6 +738,8 @@ long sd_last_disk_activity(void)
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void sd_enable(bool on)
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{
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if (sd_enabled == on)
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return; /* nothing to do */
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if(on)
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{
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CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
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@ -742,11 +793,12 @@ tCardInfo *card_get_info_target(int card_no)
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bool card_detect_target(void)
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{
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#ifdef HAVE_HOTSWAP
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/* TODO */
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return false;
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#else
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return false;
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/* TODO: add e200/c200 */
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#if defined(SANSA_FUZE)
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return !(GPIOA_PIN(2));
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#endif
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#endif
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return false;
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}
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#ifdef HAVE_HOTSWAP
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@ -754,11 +806,18 @@ void card_enable_monitoring_target(bool on)
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{
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if (on)
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{
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/* TODO */
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/* add e200v2/c200v2 here */
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#ifdef SANSA_FUZE
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/* enable isr*/
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GPIOA_IE |= (1<<2);
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#endif
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}
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else
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{
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/* TODO */
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#ifdef SANSA_FUZE
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/* edisable isr*/
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GPIOA_IE &= ~(1<<2);
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#endif
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}
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}
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#endif
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