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Define CACHEALIGN_BITS for missing ARM CPUs for later use.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28619 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Andree Buschmann 2010-11-19 07:17:20 +00:00
parent 1abc5b8ea8
commit 90a5a8a068
4 changed files with 6 additions and 1 deletions
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2
firmware/export/as3525v2.h
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@ -26,6 +26,8 @@
/* insert differences here */
#define CACHEALIGN_BITS (5)
#ifndef IRAM_SIZE /* protect in case the define name changes */
# error IRAM_SIZE not defined !
#endif

1
firmware/export/imx31l.h
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@ -38,7 +38,6 @@
#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#define NOCACHE_BASE CSD0_BASE_ADDR
/* USBOTG */

2
firmware/export/tcc77x.h
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@ -21,6 +21,8 @@
#ifndef __TCC77X_H__
#define __TCC77X_H__
#define CACHEALIGN_BITS (5)
/* General-purpose IO */
#define GPIOA (*(volatile unsigned long *)0x80000300)

2
firmware/export/tcc780x.h
View file

@ -21,6 +21,8 @@
#ifndef __TCC780X_H__
#define __TCC780X_H__
#define CACHEALIGN_BITS (5)
#define TTB_SIZE (0x4000)
/* must be 16Kb (0x4000) aligned */
#define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)