Remove some initializations that are taken care of in the bootloader or crt0 setup. Agressive timings are #if 0'd since they are unstable, but may later be added to board setup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29235 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun
parent
9a20d60bfb
commit
8f80adf4d7
1 changed files with 126 additions and 177 deletions
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@ -32,11 +32,14 @@
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#include "usb-mr500.h"
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#endif
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static unsigned short clock_arm_slow = 0xFFFF;
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static unsigned short clock_arm_fast = 0xFFFF;
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked, section(".icode")));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, section(".icode")));
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void irq_handler(void) __attribute__((interrupt ("IRQ"), section(".icode")));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), section(".icode")));
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default_interrupt(TIMER0);
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default_interrupt(TIMER1);
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@ -132,21 +135,12 @@ static void UIRQ(void)
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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unsigned short addr = IO_INTC_IRQENTRY0>>2;
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if(addr != 0)
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{
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addr--;
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irqvector[addr]();
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}
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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@ -154,18 +148,12 @@ void fiq_handler(void)
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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unsigned short addr = IO_INTC_FIQENTRY0>>2;
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if(addr != 0)
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{
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addr--;
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irqvector[addr]();
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}
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from FIQ */
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}
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void system_reboot(void)
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@ -199,20 +187,13 @@ void system_exception_wait(void)
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void system_init(void)
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{
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unsigned int vector_addr;
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/* Pin 33 is connected to a buzzer, for an annoying sound set
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* PWM0C == 0x3264
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* PWM0H == 0x1932
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* Function to 1
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* Since this is not used in the FW, set it to a normal output at a zero
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* level. */
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/* 33: output, non-inverted, no-irq, falling edge, no-chat, normal */
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dm320_set_io(33, false, false, false, false, false, 0x00);
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IO_GIO_BITCLR2 = 1<<1;
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/* Pin 1 is the power button. Right now it is setup without IRQ, but that
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* may be needed for wakeup if a different shutdown method is used. */
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/* 1: input , non-inverted, no-irq, falling edge, no-chat, normal */
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dm320_set_io(1, true, false, false, false, false, 0x00);
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/* taken from linux/arch/arm/mach-itdm320-20/irq.c */
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@ -234,45 +215,118 @@ void system_init(void)
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IO_INTC_FISEL0 = 0;
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IO_INTC_FISEL1 = 0;
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IO_INTC_FISEL2 = 0;
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/* Only initially needed clocks should be turned on */
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IO_CLK_MOD0 = CLK_MOD0_HPIB | CLK_MOD0_DSP | CLK_MOD0_SDRAMC |
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CLK_MOD0_EMIF | CLK_MOD0_INTC | CLK_MOD0_AIM |
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CLK_MOD0_AHB | CLK_MOD0_BUSC | CLK_MOD0_ARM;
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IO_CLK_MOD1 = CLK_MOD1_CPBUS;
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IO_CLK_MOD2 = CLK_MOD2_GIO;
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#if 0
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if (IO_BUSC_REVR == REVR_ES11)
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{
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/* Agressive clock setup for newer parts (ES11) - this is actually lower
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* power also.
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*/
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/* Setup the EMIF interface timings */
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/* ATA interface:
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* If this is the newer silicon the timings need to be slowed down some
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* for reliable access due to the faster ARM clock.
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*/
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/* OE width, WE width, CS width, Cycle width */
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IO_EMIF_CS3CTRL1 = (8 << 12) | (8 << 8) | (14 << 4) | 15;
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/* 14: Width (16), 12: Idles, 8: OE setup, 4: WE Setup, CS setup */
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IO_EMIF_CS3CTRL2 = (1<<14) | (1 << 12) | (3 << 8) | (3 << 4) | 1;
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/* USB interface:
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* The following EMIF timing values are from the OF:
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* IO_EMIF_CS4CTRL1 = 0x66AB;
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* IO_EMIF_CS4CTRL2 = 0x4220;
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*
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* More agressive numbers may be possible, but it depends on the clocking
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* setup.
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*/
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IO_EMIF_CS4CTRL1 = 0x66AB;
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IO_EMIF_CS4CTRL2 = 0x4220;
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/* 27 MHz input clock:
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* PLLA: 27 * 15 / 2 = 202.5 MHz
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* PLLB: 27 * 9 / 2 = 121.5 MHz (off: bit 12)
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*/
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IO_CLK_PLLA = (14 << 4) | 1;
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IO_CLK_PLLB = ( 1 << 12) | ( 8 << 4) | 1;
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/* Set the slow and fast clock speeds used for boosting
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* Slow Setup:
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* ARM div = 4 ( 50.625 MHz )
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* AHB div = 1 ( 50.625 MHz )
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* Fast Setup:
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* ARM div = 1 ( 202.5 MHz )
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* AHB div = 2 ( 101.25 MHz )
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*/
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clock_arm_slow = (0 << 8) | 3;
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clock_arm_fast = (1 << 8) | 0;
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IO_CLK_DIV0 = clock_arm_slow;
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/* SDRAM div= 2 ( 101.25 MHz )
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* AXL div = 1 ( 202.5 MHz )
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*/
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IO_CLK_DIV1 = (0 << 8) | 1;
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/* MS div = 15 ( 13.5 MHz )
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* DSP div = 4 ( 50.625 MHz - could be double, but this saves power)
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*/
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IO_CLK_DIV2 = (3 << 8) | 14;
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/* MMC div = 256 ( slow )
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* VENC div = 32 ( 843.75 KHz )
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*/
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IO_CLK_DIV3 = (31 << 8) | 255;
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/* I2C div = 1 ( 48 MHz if M48XI is running )
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* VLNQ div = 32
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*/
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IO_CLK_DIV4 = (31 << 8) | 0;
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/* Feed everything from PLLA */
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IO_CLK_SEL0=0x007E;
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IO_CLK_SEL1=0x1000;
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IO_CLK_SEL2=0x0000;
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}
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else
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#endif
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{
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/* Set the slow and fast clock speeds used for boosting
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* Slow Setup:
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* ARM div = 4 ( 87.5 MHz )
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* AHB div = 1 ( 87.5 MHz )
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* Fast Setup:
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* ARM div = 2 ( 175 MHz )
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* AHB div = 2 ( 87.5 MHz )
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*/
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clock_arm_slow = (0 << 8) | 3;
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clock_arm_fast = (1 << 8) | 1;
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}
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/* setup the clocks */
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IO_CLK_DIV0=0x0003;
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/* SDRAM Divide by 3 */
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IO_CLK_DIV1=0x0102;
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IO_CLK_DIV2=0x021F;
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IO_CLK_DIV3=0x1FFF;
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IO_CLK_DIV4=0x1F00;
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/* 27 MHz input clock:
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* PLLA = 27*11/1
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*/
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IO_CLK_PLLA=0x80A0;
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IO_CLK_PLLB=0x80C0;
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IO_CLK_SEL0=0x017E;
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IO_CLK_SEL1=0x1000;
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IO_CLK_SEL2=0x1001;
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/* need to wait before bypassing */
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IO_CLK_BYP=0x0000;
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/* turn off some unneeded modules */
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IO_CLK_MOD0 &= ~0x0018;
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IO_CLK_MOD1 = 0x0918;
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IO_CLK_MOD2 = ~0x7C58;
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/* M48XI disabled, USB buffer powerdown */
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IO_CLK_LPCTL1 = 0x11; /* I2C wodn't work with this disabled */
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/* IRQENTRY only reflects enabled interrupts */
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IO_INTC_RAW = 0;
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IO_INTC_ENTRY_TBA0 = 0;
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IO_INTC_ENTRY_TBA1 = 0;
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vector_addr = (unsigned int) irqvector;
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IO_INTC_ENTRY_TBA0 = 0;//(short) vector_addr & ~0x000F;
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IO_INTC_ENTRY_TBA1 = 0;//(short) (vector_addr >> 16);
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int i;
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/* Set interrupt priorities to predefined values */
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for(i = 0; i < 23; i++)
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DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) | (irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */
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DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) |
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(irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */
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/* Turn off all timers */
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IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
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@ -280,47 +334,12 @@ void system_init(void)
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IO_TIMER2_TMMD = CONFIG_TIMER2_TMMD_STOP;
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IO_TIMER3_TMMD = CONFIG_TIMER3_TMMD_STOP;
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#ifndef CREATIVE_ZVx
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/* set GIO26 (reset pin) to output and low */
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IO_GIO_BITCLR1=(1<<10);
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IO_GIO_DIR1&=~(1<<10);
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#endif
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uart_init();
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spi_init();
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#ifdef CREATIVE_ZVx
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dma_init();
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#endif
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#if !defined(LCD_NATIVE_WIDTH) && !defined(LCD_NATIVE_HEIGHT)
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#define LCD_NATIVE_WIDTH LCD_WIDTH
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#define LCD_NATIVE_HEIGHT LCD_HEIGHT
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#endif
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#define LCD_FUDGE LCD_NATIVE_WIDTH%32
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#define LCD_BUFFER_SIZE ((LCD_NATIVE_WIDTH+LCD_FUDGE)*LCD_NATIVE_HEIGHT*2)
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#define LCD_TTB_AREA ((LCD_BUFFER_SIZE>>19)+1)
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/* MMU initialization (Starts data and instruction cache) */
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ttb_init();
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/* Make sure everything is mapped on itself */
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map_section(0, 0, 0x1000, CACHE_NONE);
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/* Enable caching for RAM */
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map_section(CONFIG_SDRAM_START, CONFIG_SDRAM_START, MEMORYSIZE, CACHE_ALL);
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/* enable buffered writing for the framebuffer */
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map_section((int)FRAME, (int)FRAME, LCD_TTB_AREA, BUFFERED);
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#ifdef CREATIVE_ZVx
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/* mimic OF */
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map_section(0x00100000, 0x00100000, 4, CACHE_NONE);
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map_section(0x04700000, 0x04700000, 2, BUFFERED);
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map_section(0x40000000, 0x40000000, 16, CACHE_NONE);
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map_section(0x50000000, 0x50000000, 16, CACHE_NONE);
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map_section(0x60000000, 0x60000000, 16, CACHE_NONE);
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map_section(0x80000000, 0x80000000, 1, CACHE_NONE);
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#endif
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enable_mmu();
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}
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int system_memory_guard(int newmode)
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@ -332,10 +351,23 @@ int system_memory_guard(int newmode)
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (frequency == CPUFREQ_MAX) {
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IO_CLK_DIV0 = 0x0101; /* 175 MHz ARM */
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} else {
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IO_CLK_DIV0 = 0x0003; /* 87.5 MHz ARM - not much savings, about 3 mA */
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/* If these variables have not been changed since startup then boosting
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* should not be used.
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*/
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if(clock_arm_slow == 0xFFFF || clock_arm_fast == 0xFFFF)
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{
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return;
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}
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if (frequency == CPUFREQ_MAX)
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{
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IO_CLK_DIV0 = clock_arm_fast;
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FREQ = CPUFREQ_MAX;
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}
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else
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{
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IO_CLK_DIV0 = clock_arm_slow;
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FREQ = CPUFREQ_NORMAL;
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}
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}
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#endif
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@ -351,87 +383,4 @@ void udelay(int usec) {
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}
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}
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/* This function sets the specified pin up */
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void dm320_set_io (char pin_num, bool input, bool invert, bool irq, bool irqany,
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bool chat, char func_num )
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{
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volatile short *pio;
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char reg_offset; /* Holds the offset to the register */
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char shift_val; /* Holds the shift offset to the GPIO bit(s) */
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short io_val; /* Used as an intermediary to prevent glitchy
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* assignments. */
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/* Make sure this is a valid pin number */
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if( (unsigned) pin_num > 40 )
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return;
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/* Clamp the function number */
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func_num &= 0x03;
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/* Note that these are integer calculations */
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reg_offset = (pin_num / 16);
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shift_val = (pin_num - (16 * reg_offset));
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/* Handle the direction */
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/* Calculate the pointer to the direction register */
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pio = &IO_GIO_DIR0 + reg_offset;
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if(input)
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*pio |= ( 1 << shift_val );
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else
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*pio &= ~( 1 << shift_val );
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/* Handle the inversion */
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/* Calculate the pointer to the inversion register */
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pio = &IO_GIO_INV0 + reg_offset;
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if(invert)
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*pio |= ( 1 << shift_val );
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else
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*pio &= ~( 1 << shift_val );
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/* Handle the chat */
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/* Calculate the pointer to the chat register */
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pio = &IO_GIO_CHAT0 + reg_offset;
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if(chat)
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*pio |= ( 1 << shift_val );
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else
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*pio &= ~( 1 << shift_val );
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/* Handle interrupt configuration */
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if(pin_num < 16)
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{
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/* Sets whether the pin is an irq or not */
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if(irq)
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IO_GIO_IRQPORT |= (1 << pin_num );
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else
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IO_GIO_IRQPORT &= ~(1 << pin_num );
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/* Set whether this is a falling or any edge sensitive irq */
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if(irqany)
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IO_GIO_IRQEDGE |= (1 << pin_num );
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else
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IO_GIO_IRQEDGE &= ~(1 << pin_num );
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}
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/* Handle the function number */
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/* Calculate the pointer to the function register */
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reg_offset = ( (pin_num - 9) / 8 );
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shift_val = ( ((pin_num - 9) - (8 * reg_offset)) * 2 );
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if( pin_num < 9 )
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{
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reg_offset = 0;
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shift_val = 0;
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}
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/* Calculate the pointer to the function register */
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pio = &IO_GIO_FSEL0 + reg_offset;
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io_val = *pio;
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io_val &= ~( 3 << shift_val ); /* zero previous value */
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io_val |= ( func_num << shift_val ); /* Store new value */
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*pio = io_val;
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}
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