Sansa Connect: Fix reported CPU frequency
Make frequency related comments accurate. Disable UART0 clock. Change-Id: I224a3d6656ad53165dcff68ed716fa2c6863240d
This commit is contained in:
Tomasz Moń
parent
60e2cd6de9
commit
8de163b8ae
7 changed files with 66 additions and 30 deletions
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@ -501,7 +501,10 @@ void avr_hid_init(void)
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bitclr16(&IO_GIO_DIR2, (1 << 0));
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avr_hid_release();
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/* RATE = 219 (0xDB) -> 200 kHz */
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/* Master, MSB first, RATE = 219 (Bit rate = ARM clock / 2*(RATE + 1)))
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* Boosted 148.5 MHz / 440 = 337.5 kHz
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* Default 74.25 MHz / 440 = 168.75 kHz
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*/
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IO_SERIAL1_MODE = 0x6DB;
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mutex_init(&avr_mtx);
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@ -58,10 +58,10 @@ _init_board:
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/* Setup the EMIF interface timings */
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/* FLASH interface:
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* These are based on the OF setup
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* These are based on the OF setup
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*/
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/* IO_EMIF_CS0CTRL1 and
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* IO_EMIF_CS0CTRL2
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* IO_EMIF_CS0CTRL2
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*/
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mwh 0x30A00, 0x889A
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mwh 0x30A02, 0x1110
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@ -75,7 +75,7 @@ _init_board:
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mwh 0x30A0E, 0x0222
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/* IO_EMIF_CS3CTRL1 and
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* IO_EMIF_CS3CTRL2
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* IO_EMIF_CS3CTRL2
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*/
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mwh 0x30A10, 0x8899
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mwh 0x30A12, 0x5110
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@ -96,37 +96,49 @@ _init_board:
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_clock_setup:
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/* Clock initialization */
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/* Disable peripheral clocks */
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mwhm 0x3089A, 0
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mwhm 0x3089C, 0
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/* IO_CLK_BYP: Bypass the PLLs for the following changes */
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mwh 0x30894, 0x1111
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/*
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* IO_CLK_PLLA
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* IO_CLK_PLLB
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* IO_CLK_PLLA: 27 MHz * 11 / 1 = 297 MHz
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* IO_CLK_PLLB: 27 MHz
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*/
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mwhm 0x30880, 0x00A0
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mwh 0x30880, 0x10A0
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mwhm 0x30882, 0x1000
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/* IO_CLK_SEL0 */
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/* IO_CLK_SEL0: Timer 0 and 1, UART 0 and 1 from PLLIN (27 MHz) */
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mwh 0x30884, 0x0066
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/* IO_CLK_SEL1 */
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/* IO_CLK_SEL1: VENC from PLLA, OSD clock = VENC clock / 2 */
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mwhm 0x30886, 0x0003
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# IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */
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/* IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */
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mwh 0x30888, 0
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/* IO_CLK_DIV0: Set the slow clock speed for the ARM/AHB */
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/* IO_CLK_DIV0: Set the fast clock speed for the ARM/AHB
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* ARM = PLLA / 2 = 148.5 MHz
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* AHB = ARM / 2 = 74.25 MHz
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*/
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mwh 0x3088A, 0x0101
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/* IO_CLK_DIV1: Accelerator, SDRAM */
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/* IO_CLK_DIV1: Accelerator, SDRAM
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* AXL = PLLA / 2 = 148.5 MHz
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* SDRAM = PLLA / 3 = 99 MHz
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*/
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mwh 0x3088C, 0x0102
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/* IO_CLK_DIV2: DSP, MS Clock
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* OF must be booted with this value
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* DSP = PLLA / 3 = 99 MHz
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* MS = PLLA / 1 = 297 MHz
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*/
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mwhm 0x3088E, 0x0200
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# PLLA &= ~0x1000 (BIC #0x1000)
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/* PLLA &= ~0x1000 (BIC #0x1000) */
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mrh 0x30880
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bic r0, r0, #0x1000
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strh r0, [r1]
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@ -141,25 +153,27 @@ _plla_wait:
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/* IO_CLK_BYP: Enable PLL feeds */
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mwhm 0x30894, 0x0
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/* IO_CLK_MOD0 */
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/* IO_CLK_MOD0
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* Enable clocks:
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* ARM, Bus Controller, AHB, ARM internal memory, EMIF, SDRAM
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* Disable clocks:
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* ETM, E2ICE, INTC, EXTHOST, DSP, HPIB
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*/
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mwh 0x30898, 0x01A7
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/* IO_CLK_MOD1 */
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mwhm 0x3089A, 0x18
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/* IO_CLK_MOD2 */
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mwhm 0x3089C, 0x4A0
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/* IO_CLK_MOD2: Enable GIO and SIF1 clocks */
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mwhm 0x3089C, 0x0420
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/* Setup the SDRAM range on the AHB bus */
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/* SDRAMSA */
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mov r0, #0x60000
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mov r1, #0x1000000
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str r1, [r0, #0xF00]
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/* SDRAMEA: 64MB */
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mov r1, #0x5000000
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str r1, [r0, #0xF04]
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/* SDRC_REFCTL */
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mwh 0x309A8, 0
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@ -183,8 +197,11 @@ _plla_wait:
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mwhm 0x309A8, 0x0140
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/* IMGBUF SDRAM priority bit 2 set */
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mwhm 0x309BE, 0x4
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/* SDRAM refresh priority bit 1 set */
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mwhm 0x309BC, 0x2
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/* Use defined priority bits */
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ldr r0, =0x309C4
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ldr r1, [r0]
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orr r1, r1, #1
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@ -198,10 +215,11 @@ _plla_wait:
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orr r1, r1, #0x40
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strh r1, [r0]
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/* Enable auto refresh with interval (64 + 1) * 8 SDRAM clocks */
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mwhm 0x309A8, 0x0140
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/* Go through the GPIO initialization */
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/* Warning: setting some of the functions wrong will make OF unable
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/* Warning: setting some of the functions wrong will make OF unable
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to boot (freeze during startup) */
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/* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */
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mwhm 0x305A4, 0xC000
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@ -223,7 +241,7 @@ _plla_wait:
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/* IO_GIO_DIR2 */
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mwh 0x30584, 0x01FD
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/* IO_GIO_INV0 */
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mwh 0x30586, 0x0000
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@ -235,6 +253,6 @@ _plla_wait:
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bx lr
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.ltorg
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.ltorg
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.size _init_board, .-_init_board
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@ -141,7 +141,7 @@ void lcd_init_device(void)
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VENC Clock from PLLA */
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IO_CLK_SEL1 = 0x3;
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/* Set VENC Clock Division to 11
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/* Set VENC Clock Division to 11 (PLLA / 11 = 297 MHz / 11 = 27 MHz)
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OF bootloader sets division to 8, vmlinux sets it to 11 */
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IO_CLK_DIV3 = (IO_CLK_DIV3 & ~(0x1F00)) | 0xB00;
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@ -40,7 +40,9 @@ void libertas_spi_init(void)
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IO_SERIAL0_TX_ENABLE = 0x0001;
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/* SELSDEN = 0, SLVEN = 0, SIOCLR = 0, SCLKM = 1, MSB = 1, MSSEL = 0,
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* RATE = 2 -> 15MHz
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* RATE = 1 (Bit rate = ARM clock / 2*(RATE + 1)))
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* Boosted 148.5 MHz / 4 = 37.125 MHz
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* Default 74.25 MHz / 4 = 18.5625 MHz
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*/
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IO_SERIAL0_MODE = 0x0601;
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@ -805,8 +805,9 @@ int sd_init(void)
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bitclr16(&IO_CLK_MOD2, CLK_MOD2_MMC);
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bitset16(&IO_CLK_INV, CLK_INV_MMC);
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/* mmc module clock: 75 Mhz (AHB) / 2 = ~37.5 Mhz
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* (Frequencies above are taken from Sansa Connect's OF source code) */
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/* mmc module clock when boosted 74.25 Mhz (AHB) / 2 = 37.125 Mhz
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* default 37.125 (AHB) / 2 = 18.5625 MHz
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* (Frequencies above are valid for Sansa Connect) */
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IO_CLK_DIV3 = (IO_CLK_DIV3 & 0xFF00) | 0x01;
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bitset16(&IO_CLK_MOD2, CLK_MOD2_MMC);
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@ -312,7 +312,14 @@ void system_init(void)
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#endif
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{
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#ifdef SANSA_CONNECT
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/* Setting AHB divisor to 0 increases power consumption */
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/* Setting AHB divisor to 0 increases power consumption
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* Slow Setup:
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* ARM div = 4 ( 74.25 MHz )
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* AHB div = 2 ( 37.125 MHz )
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* Fast Setup:
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* ARM div = 2 ( 148.5 MHz )
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* AHB div = 2 ( 74.25 MHz )
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*/
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clock_arm_slow = (1 << 8) | 3;
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clock_arm_fast = (1 << 8) | 1;
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#else
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@ -24,10 +24,15 @@
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#include "system-arm.h"
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#include "mmu-arm.h"
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#define CPUFREQ_SLEEP 32768
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#ifdef SANSA_CONNECT
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#define CPUFREQ_DEFAULT 74250000
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#define CPUFREQ_NORMAL 74250000
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#define CPUFREQ_MAX 148500000
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#else
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#define CPUFREQ_DEFAULT 87500000
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#define CPUFREQ_NORMAL 87500000
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#define CPUFREQ_MAX 175000000
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#endif
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void udelay(int usec);
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void mdelay(int msec);
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