as3525-usb: change clock handling
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27032 a1c6a512-1295-4272-9138-f99709370657
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2a25910541
commit
7ef8b0ec4b
2 changed files with 26 additions and 47 deletions
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@ -63,7 +63,7 @@ struct usb_endpoint
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#if 0
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static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2];
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#endif
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static struct usb_ctrlrequest ep0_setup_pkt;
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static struct usb_ctrlrequest ep0_setup_pkt __attribute__((aligned(16)));
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void usb_attach(void)
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{
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@ -81,29 +81,6 @@ static void usb_delay(void)
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}
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}
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#if AS3525_MCLK_SEL != AS3525_CLK_PLLB
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static inline void usb_enable_pll(void)
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{
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CGU_COUNTB = CGU_LOCK_CNT;
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CGU_PLLB = AS3525_PLLB_SETTING;
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CGU_PLLBSUP = 0; /* enable PLLB */
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while(!(CGU_INTCTRL & CGU_PLLB_LOCK)); /* wait until PLLB is locked */
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}
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static inline void usb_disable_pll(void)
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{
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CGU_PLLBSUP = CGU_PLL_POWERDOWN;
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}
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#else
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static inline void usb_enable_pll(void)
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{
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}
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static inline void usb_disable_pll(void)
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{
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}
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#endif /* AS3525_MCLK_SEL != AS3525_CLK_PLLB */
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static void as3525v2_connect(void)
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{
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logf("usb: init as3525v2");
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@ -112,11 +89,10 @@ static void as3525v2_connect(void)
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usb_delay();
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/* 2) enable usb phy clock */
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/* PHY clock */
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#if 0
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usb_enable_pll();
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#if 1
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CGU_USB = 1<<5 /* enable */
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| (CLK_DIV(AS3525_PLLB_FREQ, 48000000) / 2) << 2
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| 2; /* source = PLLB */
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| (CLK_DIV(AS3525_PLLA_FREQ, 60000000)) << 2
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| 1; /* source = PLLA */
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#else
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CGU_USB = 0x20;
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#endif
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@ -222,8 +198,6 @@ static void reset_endpoints(void)
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/* 64 bytes packet size, active endpoint */
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DIEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp)
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| DEPCTL_usbactep;
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DCTL = DCTL_cgnpinnak | DCTL_cgoutnak;
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}
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static void core_dev_init(void)
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@ -411,10 +385,30 @@ void usb_drv_exit(void)
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disable_global_interrupts();
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}
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static void dump_regs(void)
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{
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logf("DSTS: %lx", DSTS);
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logf("DOEPCTL0=%lx", DOEPCTL(0));
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logf("DOEPTSIZ=%lx", DOEPTSIZ(0));
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logf("DIEPCTL0=%lx", DIEPCTL(0));
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logf("DOEPMSK=%lx", DOEPMSK);
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logf("DIEPMSK=%lx", DIEPMSK);
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logf("DAINTMSK=%lx", DAINTMSK);
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logf("DAINT=%lx", DAINT);
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logf("GINTSTS=%lx", GINTSTS);
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logf("GINTMSK=%lx", GINTMSK);
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logf("DCTL=%lx", DCTL);
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logf("GAHBCFG=%lx", GAHBCFG);
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logf("GUSBCFG=%lx", GUSBCFG);
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logf("DCFG=%lx", DCFG);
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logf("DTHRCTL=%lx", DTHRCTL);
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}
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static bool handle_reset(void)
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{
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logf("usb: bus reset");
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dump_regs();
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/* Clear the Remote Wakeup Signalling */
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DCTL &= ~DCTL_rmtwkupsig;
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@ -436,22 +430,6 @@ static bool handle_enum_done(void)
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logf("usb: enum done");
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/* read speed */
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logf("DSTS: %lx", DSTS);
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logf("DOEPCTL0=%lx", DOEPCTL(0));
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logf("DOEPTSIZ=%lx", DOEPTSIZ(0));
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logf("DIEPCTL0=%lx", DIEPCTL(0));
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logf("DOEPMSK=%lx", DOEPMSK);
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logf("DIEPMSK=%lx", DIEPMSK);
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logf("DAINTMSK=%lx", DAINTMSK);
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logf("DAINT=%lx", DAINT);
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logf("GINTSTS=%lx", GINTSTS);
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logf("GINTMSK=%lx", GINTMSK);
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logf("DCTL=%lx", DCTL);
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logf("GAHBCFG=%lx", GAHBCFG);
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logf("GUSBCFG=%lx", GUSBCFG);
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logf("DCFG=%lx", DCFG);
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logf("DTHRCTL=%lx", DTHRCTL);
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switch(extract(DSTS, enumspd))
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{
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case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
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@ -466,6 +444,7 @@ static bool handle_enum_done(void)
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}
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/* fixme: change EP0 mps here */
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dump_regs();
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return true;
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}
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@ -452,7 +452,7 @@
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/**
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* Parameters
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*/
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//#define USE_CUSTOM_FIFO_LAYOUT
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#define USE_CUSTOM_FIFO_LAYOUT
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#ifdef USE_CUSTOM_FIFO_LAYOUT
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/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
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