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x1000: fix broken OST2 timer prescaler

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It turns out the prescaler fields in OST_CTRL are 2 bits wide,
not 3. The programming manual (as usual) is ambiguous and its
diagram shows 2-bit wide fields, but the bit positions in the
text give a 3-bit wide field. Ingenic's Linux code and my own
testing shows that they are, in fact, 2 bits wide.

This caused the OST2 divisor to be 16 instead of 4; the OST1
divisor was correct. This means that all udelay/mdelay calls
took 4x longer than they should've. After this change the OST2
prescaler will be 4, as intended, and udelay/mdelay calls will
wait for the intended duration.

Change-Id: I2ac0a9190f49b59a840c649bf586131f5f9fde82
This commit is contained in:
Aidan MacDonald 2021-09-27 17:18:19 +01:00
parent bf54002bc1
commit 7a5130a277
3 changed files with 9 additions and 9 deletions
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4
firmware/target/mips/ingenic_x1000/fiiom3k/button-fiiom3k.c
View file

@ -45,11 +45,11 @@
#define STATE_SCROLLING 4 #define STATE_SCROLLING 4
/* Assume there's no active touch if no event is reported in this time */ /* Assume there's no active touch if no event is reported in this time */
#define AUTORELEASE_TIME (10000 * OST_TICKS_PER_US) #define AUTORELEASE_TIME (40 * 1000 * OST_TICKS_PER_US)
/* If there's no significant motion on the scrollbar for this time, /* If there's no significant motion on the scrollbar for this time,
* then report it as a button press instead */ * then report it as a button press instead */
#define SCROLL_PRESS_TIME (100000 * OST_TICKS_PER_US) #define SCROLL_PRESS_TIME (400 * 1000 * OST_TICKS_PER_US)
/* If a press on the scrollbar moves more than this during SCROLL_PRESS_TIME, /* If a press on the scrollbar moves more than this during SCROLL_PRESS_TIME,
* then we enter scrolling mode. */ * then we enter scrolling mode. */

10
firmware/target/mips/ingenic_x1000/x1000/ost.h
View file

@ -31,21 +31,21 @@
#define JT_OST_CTRL JIO_32_RW #define JT_OST_CTRL JIO_32_RW
#define JN_OST_CTRL OST_CTRL #define JN_OST_CTRL OST_CTRL
#define JI_OST_CTRL #define JI_OST_CTRL
#define BP_OST_CTRL_PRESCALE2 3 #define BP_OST_CTRL_PRESCALE2 2
#define BM_OST_CTRL_PRESCALE2 0x38 #define BM_OST_CTRL_PRESCALE2 0xc
#define BV_OST_CTRL_PRESCALE2__BY_1 0x0 #define BV_OST_CTRL_PRESCALE2__BY_1 0x0
#define BV_OST_CTRL_PRESCALE2__BY_4 0x1 #define BV_OST_CTRL_PRESCALE2__BY_4 0x1
#define BV_OST_CTRL_PRESCALE2__BY_16 0x2 #define BV_OST_CTRL_PRESCALE2__BY_16 0x2
#define BF_OST_CTRL_PRESCALE2(v) (((v) & 0x7) << 3) #define BF_OST_CTRL_PRESCALE2(v) (((v) & 0x3) << 2)
#define BFM_OST_CTRL_PRESCALE2(v) BM_OST_CTRL_PRESCALE2 #define BFM_OST_CTRL_PRESCALE2(v) BM_OST_CTRL_PRESCALE2
#define BF_OST_CTRL_PRESCALE2_V(e) BF_OST_CTRL_PRESCALE2(BV_OST_CTRL_PRESCALE2__##e) #define BF_OST_CTRL_PRESCALE2_V(e) BF_OST_CTRL_PRESCALE2(BV_OST_CTRL_PRESCALE2__##e)
#define BFM_OST_CTRL_PRESCALE2_V(v) BM_OST_CTRL_PRESCALE2 #define BFM_OST_CTRL_PRESCALE2_V(v) BM_OST_CTRL_PRESCALE2
#define BP_OST_CTRL_PRESCALE1 0 #define BP_OST_CTRL_PRESCALE1 0
#define BM_OST_CTRL_PRESCALE1 0x7 #define BM_OST_CTRL_PRESCALE1 0x3
#define BV_OST_CTRL_PRESCALE1__BY_1 0x0 #define BV_OST_CTRL_PRESCALE1__BY_1 0x0
#define BV_OST_CTRL_PRESCALE1__BY_4 0x1 #define BV_OST_CTRL_PRESCALE1__BY_4 0x1
#define BV_OST_CTRL_PRESCALE1__BY_16 0x2 #define BV_OST_CTRL_PRESCALE1__BY_16 0x2
#define BF_OST_CTRL_PRESCALE1(v) (((v) & 0x7) << 0) #define BF_OST_CTRL_PRESCALE1(v) (((v) & 0x3) << 0)
#define BFM_OST_CTRL_PRESCALE1(v) BM_OST_CTRL_PRESCALE1 #define BFM_OST_CTRL_PRESCALE1(v) BM_OST_CTRL_PRESCALE1
#define BF_OST_CTRL_PRESCALE1_V(e) BF_OST_CTRL_PRESCALE1(BV_OST_CTRL_PRESCALE1__##e) #define BF_OST_CTRL_PRESCALE1_V(e) BF_OST_CTRL_PRESCALE1(BV_OST_CTRL_PRESCALE1__##e)
#define BFM_OST_CTRL_PRESCALE1_V(v) BM_OST_CTRL_PRESCALE1 #define BFM_OST_CTRL_PRESCALE1_V(v) BM_OST_CTRL_PRESCALE1

4
utils/reggen-ng/x1000.reggen
View file

@ -807,8 +807,8 @@ node OST {
addr 0xb2000000 addr 0xb2000000
reg CTRL 0x00 { reg CTRL 0x00 {
field 5 3 PRESCALE2 { enum BY_1 0; enum BY_4 1; enum BY_16 2; } field 3 2 PRESCALE2 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
field 2 0 PRESCALE1 { enum BY_1 0; enum BY_4 1; enum BY_16 2; } field 1 0 PRESCALE1 { enum BY_1 0; enum BY_4 1; enum BY_16 2; }
} }
reg ENABLE 0x04 { reg ENABLE 0x04 {