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Gigabeat S technical correction: Fix instruction order because clean dcache operand is SBZ.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17401 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-05-07 06:13:35 +00:00
parent bc1ce741c9
commit 607b63a827
1 changed files with 1 additions and 1 deletions
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2
firmware/target/arm/imx31/crt0.S
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@ -76,8 +76,8 @@ remap_start:
mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */
tst r3, #(1 << 2) /* dcache? */
tsteq r3, #(1 << 12) /* or icache? */
mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */
mov r0, #0
mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */
mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */