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qeditor: add clock analyser for ATJ213x

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Change-Id: I5f5a3537d1ddf6b02684dd4c1dd13be862d3a918
Reviewed-on: http://gerrit.rockbox.org/1054
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This commit is contained in:
Marcin Bukat 2014-11-28 00:18:02 +01:00
parent e99c036ed1
commit 5e1381be87
3 changed files with 375 additions and 14 deletions
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159
utils/regtools/desc/regs-atj213x.xml
View file

@ -70,41 +70,96 @@
<addr name="CMU" addr="0xb0010000"/>
<reg name="COREPLL" desc="">
<addr name="COREPLL" addr="0x0"/>
<field name="RESERVED31_11" desc="" bitrange="31:11"/>
<field name="CPBY" desc="Core PLL Bypass " bitrange="10:10"/>
<field name="CPBI" desc="Core PLL Bias " bitrange="9:8"/>
<field name="CPEN" desc="Core PLL Enable " bitrange="7:7"/>
<field name="HOEN" desc="High Oscillator Enable" bitrange="6:6"/>
<field name="CPCK" desc="COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz)" bitrange="5:0"/>
</reg>
<reg name="DSPPLL" desc="">
<addr name="DSPPLL" addr="0x4"/>
<field name="RESERVED31_9" desc="" bitrange="31:9"/>
<field name="DPBI" desc="DSP PLL Bias" bitrange="8:7"/>
<field name="DPEN" desc="DSP PLL Enable" bitrange="6:6"/>
<field name="DPCK" desc="DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz)" bitrange="5:0"/>
</reg>
<reg name="AUDIOPLL" desc="">
<addr name="AUDIOPLL" addr="0x8"/>
<field name="RESERVED31_12" desc="" bitrange="31:12"/>
<field name="ADCPLL" desc="Audio PLL CLk Control" bitrange="11:11"/>
<field name="ADCCLK" desc="ADC Clock Divisor, output is FS*256" bitrange="10:8"/>
<field name="RESERVED7" desc="" bitrange="7:7"/>
<field name="APBI" desc="Audio PLL Bias" bitrange="6:5"/>
<field name="APEN" desc="Audio PLL Enable" bitrange="4:4"/>
<field name="DACPLL" desc="DAC PLL CLk Control" bitrange="3:3"/>
<field name="DACCLK" desc="DAC Clock Divisor, output is FS*256" bitrange="2:0"/>
</reg>
<reg name="BUSCLK" desc="">
<reg name="BUSCLK" desc="Bus CLK Control Register">
<addr name="BUSCLK" addr="0xc"/>
<field name="KEYE" desc="Key Wakeup Enable" bitrange="31:31"/>
<field name="ALME" desc="Alarm Wakeup Enable" bitrange="30:30"/>
<field name="SIRE" desc="SIRQ Wakeup Enable" bitrange="29:29"/>
<field name="RESERVED28" desc="" bitrange="28:28"/>
<field name="USBE" desc="Usb Wakeup Enable" bitrange="27:27"/>
<field name="RESERVED26:12" desc="" bitrange="26:12"/>
<field name="PCLKDIV" desc="Peripheral CLK Divisor" bitrange="11:8"/>
<field name="CORECLKS" desc="CPU Clock Selection" bitrange="7:6"/>
<field name="SCLKDIV" desc="System Clock Divisor" bitrange="5:4"/>
<field name="CCLKDIV" desc="CPU Clock Divisor" bitrange="3:2"/>
<field name="DCEN" desc="Core CLK DC Enable" bitrange="1:1"/>
</reg>
<reg name="SDRCLK" desc="">
<reg name="SDRCLK" desc="SDRAM Interface CLK Control Register">
<addr name="SDRCLK" addr="0x10"/>
<field name="RESERVED31_2" desc="" bitrange="31:2"/>
<field name="SDRDIV" desc="" bitrange="1:0"/>
</reg>
<reg name="NANDCLK" desc="">
<reg name="NANDCLK" desc="NAND Interface CLK Control Register">
<addr name="NANDCLK" addr="0x18"/>
<field name="RESERVED31_4" desc="" bitrange="31:4"/>
<field name="NANDDIV" desc="" bitrange="3:0"/>
</reg>
<reg name="SDCLK" desc="">
<reg name="SDCLK" desc="SD Interface CLK Control Register&#10;">
<addr name="SDCLK" addr="0x1c"/>
<field name="RESERVED31_6" desc="" bitrange="31:6"/>
<field name="CKEN" desc="SD Interface Clock Enable" bitrange="5:5"/>
<field name="D128" desc="Enable Divide 128 circuit" bitrange="4:4"/>
<field name="SDDIV" desc="" bitrange="3:0"/>
</reg>
<reg name="MHACLK" desc="">
<reg name="MHACLK" desc="MHA CLK Control Register">
<addr name="MHACLK" addr="0x20"/>
<field name="RESERVED31_4" desc="" bitrange="31:4"/>
<field name="MHADIV" desc="" bitrange="3:0"/>
</reg>
<reg name="UART2CLK" desc="">
<reg name="UART2CLK" desc="Uart2 CLK Control Register">
<addr name="UART2CLK" addr="0x2c"/>
<field name="RESERVED31_17" desc="" bitrange="31:17"/>
<field name="U2EN" desc="Uart2 Clock Enable &#10;" bitrange="16:16"/>
<field name="UART2DIV" desc="" bitrange="15:0"/>
</reg>
<reg name="DMACLK" desc="">
<reg name="DMACLK" desc="DMA CLK Control Register">
<addr name="DMACLK" addr="0x30"/>
<field name="RESERVED31_4" desc="" bitrange="31:4"/>
<field name="D7EN" desc="DMA 7 (Special Channel) Clock Enable" bitrange="3:3"/>
<field name="D6EN" desc="DMA 6 (Special Channel) Clock Enable" bitrange="2:2"/>
<field name="D5EN" desc="DMA 5 (Special Channel) Clock Enable" bitrange="1:1"/>
<field name="D4EN" desc="DMA 4 (Special Channel) Clock Enable" bitrange="0:0"/>
</reg>
<reg name="FMCLK" desc="">
<reg name="FMCLK" desc="FM CLK Control Register">
<addr name="FMCLK" addr="0x34"/>
<field name="RESERVED31_6" desc="" bitrange="31:6"/>
<field name="BCKE" desc="PWM Back Light clock Enable" bitrange="5:5"/>
<field name="BCKS" desc="Back Light CLK source select" bitrange="4:4"/>
<field name="BCKCON" desc="Divided PWM Back Light Special Clock Control" bitrange="3:2"/>
<field name="CLKS" desc="FM Clock Output Selection" bitrange="1:1"/>
<field name="OUTE" desc="FM Clock Output Enable (From Test Pin)" bitrange="0:0"/>
</reg>
<reg name="MCACLK" desc="">
<reg name="MCACLK" desc="MCA CLK Control Register">
<addr name="MCACLK" addr="0x38"/>
<field name="RESERVED31_4" desc="" bitrange="31:4"/>
<field name="MCADIV" desc="" bitrange="3:0"/>
</reg>
<reg name="DEVCLKEN" desc="">
<reg name="DEVCLKEN" desc="Device CLK Control Register">
<addr name="DEVCLKEN" addr="0x80"/>
<field name="RESERVED31_27" desc="" bitrange="31:27"/>
<field name="GPIO" desc="" bitrange="26:26"/>
@ -133,8 +188,36 @@
<field name="YUV" desc="" bitrange="1:1"/>
<field name="RESERVED0" desc="" bitrange="0:0"/>
</reg>
<reg name="DEVRST" desc="">
<reg name="DEVRST" desc="Device Reset Control Register">
<addr name="DEVRST" addr="0x84"/>
<field name="RESERVED31" desc="" bitrange="31:31"/>
<field name="GPIO" desc="" bitrange="30:30"/>
<field name="KEY" desc="" bitrange="29:29"/>
<field name="RESERVED28" desc="" bitrange="28:28"/>
<field name="I2C" desc="" bitrange="27:27"/>
<field name="UART" desc="" bitrange="26:26"/>
<field name="RESERVED25_23" desc="" bitrange="25:23"/>
<field name="ADC" desc="" bitrange="22:22"/>
<field name="DAC" desc="" bitrange="21:21"/>
<field name="DSPC" desc="DSP control block reset" bitrange="20:20"/>
<field name="INTC" desc="" bitrange="19:19"/>
<field name="RTC" desc="" bitrange="18:18"/>
<field name="PMU" desc="" bitrange="17:17"/>
<field name="RESERVED16_14" desc="" bitrange="16:14"/>
<field name="DSPM" desc="SRAM DSP MEM reset" bitrange="13:13"/>
<field name="TVENC" desc="" bitrange="12:12"/>
<field name="YUV" desc="" bitrange="11:11"/>
<field name="MCA" desc="" bitrange="10:10"/>
<field name="USB" desc="" bitrange="9:9"/>
<field name="RESERVED8" desc="" bitrange="8:8"/>
<field name="MHA" desc="" bitrange="7:7"/>
<field name="SD" desc="" bitrange="6:6"/>
<field name="NAND" desc="" bitrange="5:5"/>
<field name="RESERVED4" desc="" bitrange="4:4"/>
<field name="DMAC" desc="" bitrange="3:3"/>
<field name="PCNT" desc="" bitrange="2:2"/>
<field name="RESERVED1" desc="" bitrange="1:1"/>
<field name="SDR" desc="SDRAM Control register and SDRAM block Reset" bitrange="0:0"/>
</reg>
</dev>
<dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0">
@ -369,8 +452,56 @@
</reg>
</dev>
<dev name="I2C" long_name="" desc="" version="1.0">
<addr name="I2C0" addr="0xb0180000"/>
<addr name="I2C1" addr="0xb0180020"/>
<addr name="I2C1" addr="0xb0180000"/>
<addr name="I2C2" addr="0xb0180020"/>
<reg name="CTL" desc="">
<addr name="CTL" addr="0x0"/>
<field name="RESERVED31_9" desc="" bitrange="31:9"/>
<field name="PUEN" desc="nternal Pull-up Resistor (4.7k) Enable" bitrange="8:8"/>
<field name="EN" desc="Block enable" bitrange="7:7"/>
<field name="SIE" desc="START Condition Generates IRQ Enable (only for slave mode)" bitrange="6:6"/>
<field name="IRQE" desc="IRQ Enable" bitrange="5:5"/>
<field name="MS" desc="Mode select" bitrange="4:4">
<value name="MASTER" value="0x0" desc=""/>
<value name="SLAVE" value="0x0" desc=""/>
</field>
<field name="GBCC" desc="Generating Bus Control Condition (only for master mode)" bitrange="3:2">
<value name="NOP" value="0x0" desc=""/>
<value name="START" value="0x1" desc=""/>
<value name="STOP" value="0x2" desc=""/>
<value name="REPEATED_START" value="0x3" desc=""/>
</field>
<field name="RB" desc="Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of&#10;the whole transfer.&#10;" bitrange="1:1"/>
<field name="GRAS" desc="Generating/Receiving Acknowledge Signal" bitrange="0:0"/>
</reg>
<reg name="CLKDIV" desc="">
<addr name="CLKDIV" addr="0x4"/>
<field name="RESERVED31_8" desc="" bitrange="31:8"/>
<field name="CLKDIV" desc="Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16)&#10;" bitrange="7:0"/>
</reg>
<reg name="STAT" desc="">
<addr name="STAT" addr="0x8"/>
<field name="RESERVED31_8" desc="" bitrange="31:8"/>
<field name="TRC" desc="Transmit/Receive Complete Bit" bitrange="7:7"/>
<field name="STPD" desc="STOP Detect Bit " bitrange="6:6"/>
<field name="STAD" desc="START Detect Bit" bitrange="5:5"/>
<field name="RWST" desc="Read/Write Status Bit (only for Slave mode)" bitrange="4:4"/>
<field name="LBST" desc="Last Byte Status Bit" bitrange="3:3"/>
<field name="IRQP" desc="IRQ Pending Bit" bitrange="2:2"/>
<field name="OVST" desc="Overflow Status Bit" bitrange="1:1"/>
<field name="WCO" desc="Writing Collision Bit" bitrange="0:0"/>
</reg>
<reg name="ADDR" desc="">
<addr name="ADDR" addr="0xc"/>
<field name="RESERVED31_8" desc="" bitrange="31:8"/>
<field name="SDAD" desc="Slave Device Address" bitrange="7:1"/>
<field name="RWCM" desc="Read/Write Control or Match" bitrange="0:0"/>
</reg>
<reg name="DAT" desc="">
<addr name="DAT" addr="0x10"/>
<field name="RESERVED31_8" desc="" bitrange="31:8"/>
<field name="TXRXDAT" desc="Transmit/Receive Data" bitrange="7:0"/>
</reg>
</dev>
<dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0">
<addr name="INTC" addr="0xb0020000"/>
@ -688,6 +819,8 @@
</reg>
<reg name="EN" desc="">
<addr name="EN" addr="0x8"/>
<field name="RESERVED31_1" desc="" bitrange="31:1"/>
<field name="EN" desc="" bitrange="0:0"/>
</reg>
<reg name="CMD" desc="">
<addr name="CMD" addr="0xc"/>

229
utils/regtools/qeditor/std_analysers.cpp
View file

@ -33,7 +33,7 @@ QWidget *ClockAnalyser::GetWidget()
bool ClockAnalyser::SupportSoc(const QString& soc_name)
{
return soc_name == "imx233" || soc_name == "rk27xx";
return (soc_name == "imx233" || soc_name == "rk27xx" || soc_name == "atj213x");
}
QString ClockAnalyser::GetFreq(unsigned freq)
@ -84,10 +84,237 @@ void ClockAnalyser::FillTree()
m_tree_widget->clear();
if(m_soc.GetSoc().name == "imx233") FillTreeIMX233();
else if(m_soc.GetSoc().name == "rk27xx") FillTreeRK27XX();
else if(m_soc.GetSoc().name == "atj213x") FillTreeATJ213X();
m_tree_widget->expandAll();
m_tree_widget->resizeColumnToContents(0);
}
void ClockAnalyser::FillTreeATJ213X()
{
soc_word_t pllbypass, pllclk, en, coreclks, tmp0, tmp1, tmp2, tmp3;
BackendHelper helper(m_io_backend, m_soc);
// system oscillators 32.768k and 24M
QTreeWidgetItem *losc_clk = AddClock(0, "losc clk", 32768);
QTreeWidgetItem *hosc_clk = AddClock(0, "hosc clk", 24000000);
// core pll
QTreeWidgetItem *corepll = 0;
if (helper.ReadRegisterField("CMU", "COREPLL", "CPEN", en) &&
helper.ReadRegisterField("CMU", "COREPLL", "CPBY", pllbypass) &&
helper.ReadRegisterField("CMU", "COREPLL", "CPCK", pllclk))
{
corepll = AddClock(hosc_clk, "core pll", en ? FROM_PARENT : DISABLED,
pllbypass ? 1 : pllclk, pllbypass ? 1 : 4);
}
else
{
corepll = AddClock(hosc_clk, "core pll", INVALID);
}
// dsp pll
QTreeWidgetItem *dsppll = 0;
if (helper.ReadRegisterField("CMU", "DSPPLL", "DPEN", en) &&
helper.ReadRegisterField("CMU", "DSPPLL", "DPCK", pllclk))
{
dsppll = AddClock(hosc_clk, "dsp pll", en ? FROM_PARENT : DISABLED,
pllbypass ? 1 : pllclk, pllbypass ? 1 : 4);
}
else
{
dsppll = AddClock(hosc_clk, "dsp pll", INVALID);
}
// audio pll
QTreeWidgetItem *adcpll = 0;
QTreeWidgetItem *dacpll = 0;
if (helper.ReadRegisterField("CMU", "AUDIOPLL", "APEN", en) &&
helper.ReadRegisterField("CMU", "AUDIOPLL", "ADCCLK", tmp0) &&
helper.ReadRegisterField("CMU", "AUDIOPLL", "DACCLK", tmp1))
{
if (en)
{
adcpll = AddClock(hosc_clk, "audio adc pll", tmp0 ? 22579200 : 24576000);
dacpll = AddClock(hosc_clk, "audio dac pll", tmp1 ? 22579200 : 24576000);
}
else
{
adcpll = AddClock(hosc_clk, "audio adc pll", DISABLED);
dacpll = AddClock(hosc_clk, "audio dac pll", DISABLED);
}
}
else
{
adcpll = AddClock(hosc_clk, "audio adc pll", INVALID);
dacpll = AddClock(hosc_clk, "audio dac pll", INVALID);
}
// audio clocks
QTreeWidgetItem *adcclk = 0;
QTreeWidgetItem *dacclk = 0;
if (helper.ReadRegisterField("CMU", "AUDIOPLL", "ADCCLK", tmp0) &&
helper.ReadRegisterField("CMU", "AUDIOPLL", "DACCLK", tmp1))
{
adcclk = AddClock(adcpll, "audio adc clk", FROM_PARENT, 1, tmp0+1);
dacclk = AddClock(dacpll, "audio dac clk", FROM_PARENT, 1, tmp1+1);
}
else
{
adcclk = AddClock(adcpll, "audio adc clk", INVALID);
dacclk = AddClock(adcpll, "audio dac clk", INVALID);
}
// cpu clock
QTreeWidgetItem *cpuclk = 0;
if (helper.ReadRegisterField("CMU", "BUSCLK", "CORECLKS", coreclks) &&
helper.ReadRegisterField("CMU", "BUSCLK", "CCLKDIV", tmp0))
{
if (coreclks == 0)
cpuclk = AddClock(losc_clk, "cpu clk", FROM_PARENT, 1, tmp0+1);
else if (coreclks == 1)
cpuclk = AddClock(hosc_clk, "cpu clk", FROM_PARENT, 1, tmp0+1);
else if (coreclks == 2)
cpuclk = AddClock(corepll, "cpu clk", FROM_PARENT, 1, tmp0+1);
else
cpuclk = AddClock(corepll, "cpu clk", INVALID);
}
else
{
cpuclk = AddClock(corepll, "cpu clk", INVALID);
}
// system clock
QTreeWidgetItem *sysclk = 0;
if (helper.ReadRegisterField("CMU", "BUSCLK", "SCLKDIV", tmp0))
sysclk = AddClock(cpuclk, "system clk", FROM_PARENT, 1, tmp0+1);
else
sysclk = AddClock(cpuclk, "system clk", INVALID);
// peripherial clk
QTreeWidgetItem *pclk = 0;
if (helper.ReadRegisterField("CMU", "BUSCLK", "PCLKDIV", tmp0))
pclk = AddClock(sysclk, "peripherial clk", FROM_PARENT, 1, tmp0 ? tmp0+1 : 2);
else
pclk = AddClock(sysclk, "peripherial clk", INVALID);
// sdram clk
QTreeWidgetItem *sdrclk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "SDRC", en) &&
helper.ReadRegisterField("CMU", "DEVCLKEN", "SDRM", tmp0) &&
helper.ReadRegisterField("SDR", "EN", "EN", tmp1) &&
helper.ReadRegisterField("CMU", "SDRCLK", "SDRDIV", tmp2))
{
en &= tmp0 & tmp1;
sdrclk = AddClock(sysclk, "sdram clk", en ? FROM_PARENT: DISABLED, 1, tmp2+1);
}
else
sdrclk = AddClock(sysclk, "sdram clk", INVALID);
// nand clk
QTreeWidgetItem *nandclk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "NAND", en) &&
helper.ReadRegisterField("CMU", "NANDCLK", "NANDDIV", tmp0))
nandclk = AddClock(corepll, "nand clk", en ? FROM_PARENT : DISABLED, 1, tmp0+1);
else
nandclk = AddClock(corepll, "nand clk", INVALID);
// sd clk
QTreeWidgetItem *sdclk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "SD", tmp0) &&
helper.ReadRegisterField("CMU", "SDCLK", "CKEN" , tmp1) &&
helper.ReadRegisterField("CMU", "SDCLK", "D128" , tmp2) &&
helper.ReadRegisterField("CMU", "SDCLK", "SDDIV" , tmp3))
{
en = tmp0 & tmp1;
sdclk = AddClock(corepll, "sd clk", en ? FROM_PARENT : DISABLED,
1, tmp2 ? 128*(tmp3+1) : (tmp3));
}
else
sdclk = AddClock(corepll, "sd clk", INVALID);
// mha clk
QTreeWidgetItem *mhaclk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "MHA", en) &&
helper.ReadRegisterField("CMU", "MHACLK", "MHADIV", tmp1))
mhaclk = AddClock(corepll, "mha clk", en ? FROM_PARENT : DISABLED,
1, tmp1+1);
else
mhaclk = AddClock(corepll, "mha clk", INVALID);
// mca clk
QTreeWidgetItem *mcaclk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "MCA", en) &&
helper.ReadRegisterField("CMU", "MCACLK", "MCADIV", tmp1))
mcaclk = AddClock(corepll, "mca clk", en ? FROM_PARENT : DISABLED,
1, tmp1+1);
else
mcaclk = AddClock(corepll, "mca clk", INVALID);
// backlight pwm
QTreeWidgetItem *pwmclk = 0;
if (helper.ReadRegisterField("CMU", "FMCLK", "BCKE", en) &&
helper.ReadRegisterField("CMU", "FMCLK", "BCKS", tmp1) &&
helper.ReadRegisterField("CMU", "FMCLK", "BCKCON", tmp2))
{
if (tmp1)
{
// HOSC/8 input clk
pwmclk = AddClock(hosc_clk, "pwm clk", en ? FROM_PARENT : DISABLED,
1, 3*(tmp2+1));
}
else
{
// LOSC input clk
pwmclk = AddClock(losc_clk, "pwm clk", en ? FROM_PARENT : DISABLED,
1, tmp2+1);
}
}
else
pwmclk = AddClock(losc_clk, "pwm clk", INVALID);
// i2c clk
QTreeWidgetItem *i2c1clk = 0;
QTreeWidgetItem *i2c2clk = 0;
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "I2C", en) &&
helper.ReadRegisterField("I2C1", "CTL", "EN", tmp0) &&
helper.ReadRegisterField("I2C1", "CLKDIV", "CLKDIV", tmp1))
{
en &= tmp0;
i2c1clk = AddClock(pclk, "i2c1 clk", en ? FROM_PARENT : DISABLED,
1, 16*(tmp1+1));
}
else
{
i2c1clk = AddClock(pclk, "i2c1 clk", INVALID);
}
if (helper.ReadRegisterField("CMU", "DEVCLKEN", "I2C", en) &&
helper.ReadRegisterField("I2C2", "CTL", "EN", tmp0) &&
helper.ReadRegisterField("I2C2", "CLKDIV", "CLKDIV", tmp1))
{
en &= tmp0;
i2c2clk = AddClock(pclk, "i2c2 clk", en ? FROM_PARENT : DISABLED,
1, 16*(tmp1+1));
}
else
{
i2c2clk = AddClock(pclk, "i2c2 clk", INVALID);
}
Q_UNUSED(dsppll);
Q_UNUSED(adcclk);
Q_UNUSED(dacclk);
Q_UNUSED(sdrclk);
Q_UNUSED(nandclk);
Q_UNUSED(sdclk);
Q_UNUSED(mhaclk);
Q_UNUSED(mcaclk);
Q_UNUSED(pwmclk);
Q_UNUSED(i2c1clk);
Q_UNUSED(i2c2clk);
}
void ClockAnalyser::FillTreeRK27XX()
{
soc_word_t value, value2, value3, value4;

1
utils/regtools/qeditor/std_analysers.h
View file

@ -42,6 +42,7 @@ private:
void FillTree();
void FillTreeIMX233();
void FillTreeRK27XX();
void FillTreeATJ213X();
private:
QGroupBox *m_group;