iPod Classic: update timer API using 32-bit timers.
Change-Id: I49dab8ae955a339ad0a27402fa21caa411c4ecf6 Reviewed-on: http://gerrit.rockbox.org/1032 Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This commit is contained in:
Cástor Muñoz
Marcin Bukat
parent
229a02a4ee
commit
57969698ce
3 changed files with 69 additions and 47 deletions
|
|
@ -28,8 +28,6 @@
|
|||
#define REG16_PTR_T volatile uint16_t *
|
||||
#define REG32_PTR_T volatile uint32_t *
|
||||
|
||||
#define TIMER_FREQ 54000000
|
||||
|
||||
#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
|
||||
|
||||
#define DRAM_ORIG 0x08000000
|
||||
|
|
@ -65,6 +63,34 @@
|
|||
|
||||
|
||||
/////TIMER/////
|
||||
/* 16/32-bit timers:
|
||||
*
|
||||
* - Timers A..D: 16-bit counter, very similar to 16-bit timers described
|
||||
* in S5L8700 DS, it seems that the timers C and D are disabled or not
|
||||
* implemented.
|
||||
*
|
||||
* - Timers E..H: 32-bit counter, they are like 16-bit timers, but the
|
||||
* interrupt status for all 32-bit timers is located in TSTAT register.
|
||||
*
|
||||
* - Clock source configuration:
|
||||
*
|
||||
* TCON[10:8] (Tx_CS) TCON[6]=0 TCON[6]=1
|
||||
* ------------------ --------- ---------
|
||||
* 000 PCLK / 2 ECLK / 2
|
||||
* 001 PCLK / 4 ECLK / 4
|
||||
* 010 PCLK / 16 ECLK / 16
|
||||
* 011 PCLK / 64 ECLK / 64
|
||||
* 10x (timers E..H) PCLK ECLK
|
||||
* 10x (timers A..D) Ext. Clock 0 Ext. Clock 0
|
||||
* 11x Ext. Clock 1 Ext. Clock 1
|
||||
*
|
||||
* On Classic:
|
||||
* - Ext. Clock 0: not connected or disabled
|
||||
* - Ext. Clock 1: 32768 Hz, external OSC1?, PMU?
|
||||
* - ECLK: 12 MHz, external OSC0?
|
||||
*/
|
||||
#define TIMER_FREQ 12000000 /* ECLK */
|
||||
|
||||
#define TACON (*((uint32_t volatile*)(0x3C700000)))
|
||||
#define TACMD (*((uint32_t volatile*)(0x3C700004)))
|
||||
#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
|
||||
|
|
@ -113,6 +139,7 @@
|
|||
#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
|
||||
#define THPRE (*((uint32_t volatile*)(0x3C700110)))
|
||||
#define THCNT (*((uint32_t volatile*)(0x3C700114)))
|
||||
#define TSTAT (*((uint32_t volatile*)(0x3C700118)))
|
||||
#define USEC_TIMER TECNT
|
||||
|
||||
|
||||
|
|
@ -816,6 +843,7 @@ struct dma_lli
|
|||
|
||||
|
||||
/////INTERRUPTS/////
|
||||
#define IRQ_TIMER32 7
|
||||
#define IRQ_TIMER 8
|
||||
#define IRQ_USB_FUNC 19
|
||||
#define IRQ_DMAC(d) 16 + d
|
||||
|
|
|
|||
|
|
@ -39,15 +39,14 @@ default_interrupt(INT_IRQ3);
|
|||
default_interrupt(INT_IRQ4);
|
||||
default_interrupt(INT_IRQ5);
|
||||
default_interrupt(INT_IRQ6);
|
||||
default_interrupt(INT_IRQ7);
|
||||
default_interrupt(INT_TIMERA);
|
||||
default_interrupt(INT_TIMERB);
|
||||
default_interrupt(INT_TIMERC);
|
||||
default_interrupt(INT_TIMERD);
|
||||
default_interrupt(INT_TIMERE);
|
||||
default_interrupt(INT_TIMERE); /* IRQ7: 32-bit timers */
|
||||
default_interrupt(INT_TIMERF);
|
||||
default_interrupt(INT_TIMERG);
|
||||
default_interrupt(INT_TIMERH);
|
||||
default_interrupt(INT_TIMERA); /* IRQ8: 16-bit timers */
|
||||
default_interrupt(INT_TIMERB);
|
||||
default_interrupt(INT_TIMERC);
|
||||
default_interrupt(INT_TIMERD);
|
||||
default_interrupt(INT_IRQ9);
|
||||
default_interrupt(INT_IRQ10);
|
||||
default_interrupt(INT_IRQ11);
|
||||
|
|
@ -129,9 +128,16 @@ void INT_TIMER()
|
|||
if (TBCON & (TBCON >> 4) & 0x7000) INT_TIMERB();
|
||||
if (TCCON & (TCCON >> 4) & 0x7000) INT_TIMERC();
|
||||
if (TDCON & (TDCON >> 4) & 0x7000) INT_TIMERD();
|
||||
if (TFCON & (TFCON >> 4) & 0x7000) INT_TIMERF();
|
||||
if (TGCON & (TGCON >> 4) & 0x7000) INT_TIMERG();
|
||||
if (THCON & (THCON >> 4) & 0x7000) INT_TIMERH();
|
||||
}
|
||||
|
||||
void INT_TIMER32(void) ICODE_ATTR;
|
||||
void INT_TIMER32()
|
||||
{
|
||||
uint32_t tstat = TSTAT;
|
||||
/*if ((TECON >> 12) & 0x7 & (tstat >> 24)) INT_TIMERE();*/
|
||||
if ((TFCON >> 12) & 0x7 & (tstat >> 16)) INT_TIMERF();
|
||||
if ((TGCON >> 12) & 0x7 & (tstat >> 8)) INT_TIMERG();
|
||||
if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH();
|
||||
}
|
||||
|
||||
void INT_DMAC0(void) ICODE_ATTR;
|
||||
|
|
@ -164,7 +170,7 @@ void INT_DMAC1()
|
|||
|
||||
static void (* const irqvector[])(void) =
|
||||
{
|
||||
INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_IRQ7,
|
||||
INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_TIMER32,
|
||||
INT_TIMER,INT_IRQ9,INT_IRQ10,INT_IRQ11,INT_IRQ12,INT_IRQ13,INT_IRQ14,INT_IRQ15,
|
||||
INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL,
|
||||
INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_ATA,INT_IRQ30,INT_IRQ31,
|
||||
|
|
@ -220,6 +226,7 @@ void system_init(void)
|
|||
VIC0INTENABLE = 1 << IRQ_WHEEL;
|
||||
VIC0INTENABLE = 1 << IRQ_ATA;
|
||||
VIC1INTENABLE = 1 << (IRQ_MMC - 32);
|
||||
VIC0INTENABLE = 1 << IRQ_TIMER32;
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
|
|
|
|||
|
|
@ -26,13 +26,11 @@
|
|||
#include "system.h"
|
||||
#include "timer.h"
|
||||
|
||||
//TODO: This needs calibration once we figure out the clocking
|
||||
|
||||
void INT_TIMERC(void)
|
||||
void INT_TIMERF(void)
|
||||
{
|
||||
/* clear interrupt */
|
||||
TCCON = TCCON;
|
||||
|
||||
TSTAT = (0x07 << 16);
|
||||
|
||||
if (pfn_timer != NULL) {
|
||||
pfn_timer();
|
||||
}
|
||||
|
|
@ -40,12 +38,8 @@ void INT_TIMERC(void)
|
|||
|
||||
bool timer_set(long cycles, bool start)
|
||||
{
|
||||
static const int cs_table[] = {1, 2, 4, 6};
|
||||
int prescale, cs;
|
||||
long count;
|
||||
|
||||
/* stop and clear timer */
|
||||
TCCMD = (1 << 1); /* TD_CLR */
|
||||
/* stop timer */
|
||||
TFCMD = (0 << 0); /* TF_ENABLE */
|
||||
|
||||
/* optionally unregister any previously registered timer user */
|
||||
if (start) {
|
||||
|
|
@ -55,40 +49,33 @@ bool timer_set(long cycles, bool start)
|
|||
}
|
||||
}
|
||||
|
||||
/* scale the count down with the clock select */
|
||||
for (cs = 0; cs < 4; cs++) {
|
||||
count = cycles >> cs_table[cs];
|
||||
if ((count < 65536) || (cs == 3)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* scale the count down with the prescaler */
|
||||
prescale = 1;
|
||||
while (count >= 65536) {
|
||||
count >>= 1;
|
||||
prescale <<= 1;
|
||||
}
|
||||
/* There is an odd behaviour when the 32-bit timers are launched
|
||||
for the first time, the interrupt status bits are set and an
|
||||
unexpected interrupt is generated if they are enabled. A way to
|
||||
workaround this is to write the data registers before clearing
|
||||
the counter. */
|
||||
TFDATA0 = cycles;
|
||||
TFCMD = (1 << 1); /* TF_CLR */
|
||||
|
||||
/* configure timer */
|
||||
TCCON = (1 << 12) | /* TD_INT0_EN */
|
||||
(cs << 8) | /* TS_CS */
|
||||
(0 << 4); /* TD_MODE_SEL, 0 = interval mode */
|
||||
TCPRE = prescale - 1;
|
||||
TCDATA0 = count;
|
||||
TCCMD = (1 << 0); /* TD_ENABLE */
|
||||
|
||||
TFCON = (1 << 12) | /* TF_INT0_EN */
|
||||
(4 << 8) | /* TF_CS, 4 = ECLK / 1 */
|
||||
(1 << 6) | /* use ECLK (12MHz) */
|
||||
(0 << 4); /* TF_MODE_SEL, 0 = interval mode */
|
||||
TFPRE = 0; /* no prescaler */
|
||||
|
||||
TFCMD = (1 << 0); /* TF_ENABLE */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool timer_start(void)
|
||||
{
|
||||
TCCMD = (1 << 0); /* TD_ENABLE */
|
||||
TFCMD = (1 << 0); /* TF_ENABLE */
|
||||
return true;
|
||||
}
|
||||
|
||||
void timer_stop(void)
|
||||
{
|
||||
TCCMD = (0 << 0); /* TD_ENABLE */
|
||||
TFCMD = (0 << 0); /* TF_ENABLE */
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue