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rk27xx: implement system_init()

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For now it contains explicit SDRAM setup, cutting clock for unused
modules and turning off unused PLLs. This improves slightly mem
throughput as well as saves quite a bit of power.

Change-Id: I19a2827ac90a6868856c676fbe1e051c42f0d608
This commit is contained in:
Marcin Bukat 2012-03-22 23:45:27 +01:00
parent 2e03c2a8b3
commit 5513c6db56
1 changed files with 29 additions and 0 deletions
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29
firmware/target/arm/rk27xx/system-rk27xx.c
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@ -117,6 +117,34 @@ void fiq_dummy(void)
void system_init(void)
{
/* SDRAM tweaks */
MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */
MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */
MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */
MCSDR_T_RP = 1; /* precharge period */
MCSDR_T_RCD = 1; /* active to RD/WR delay */
/* turn off clock for unused modules */
SCU_CLKCFG |= (1<<31) | /* WDT pclk */
(1<<30) | /* RTC pclk */
(1<<26) | /* HS_ADC clock */
(1<<25) | /* HS_ADC HCLK */
(1<<21) | /* SPI clock */
(1<<19) | /* UART1 clock */
(1<<18) | /* UART0 clock */
(1<<15) | /* VIP clock */
(1<<14) | /* VIP HCLK */
(1<<13) | /* LCDC clock */
(1<<9) | /* NAND HCLK */
(1<<5) | /* USB host HCLK */
(1<<1) | /* DSP clock */
(1<<0); /* OTP clock (dunno what it is */
/* turn off DSP pll */
SCU_PLLCON2 |= (1<<22);
/* turn off codec pll */
SCU_PLLCON3 |= (1<<22);
return;
}
@ -124,6 +152,7 @@ void system_init(void)
void system_reboot(void)
{
/* use Watchdog to reset */
SCU_CLKCFG &= ~(1<<31);
WDTLR = 1;
WDTCON = (1<<4) | (1<<3);