Meg F/X: Radically changing divider settings messed up the fake sleep in the bootloader. They aren't reset even after powering off. Make sure they are always specified. Move that code to target tree as well.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19358 a1c6a512-1295-4272-9138-f99709370657
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8289b966b8
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2 changed files with 29 additions and 14 deletions
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@ -245,19 +245,8 @@ void timeout_register(struct timeout *tmo, timeout_cb_type callback,
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void sleep(int ticks)
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{
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#if CONFIG_CPU == S3C2440 && defined(BOOTLOADER)
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volatile int counter;
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TCON &= ~(1 << 20); // stop timer 4
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// TODO: this constant depends on dividers settings inherited from
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// firmware. Set them explicitly somwhere.
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TCNTB4 = 12193 * ticks / HZ;
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TCON |= 1 << 21; // set manual bit
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TCON &= ~(1 << 21); // reset manual bit
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TCON &= ~(1 << 22); //autoreload Off
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TCON |= (1 << 20); // start timer 4
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do {
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counter = TCNTO4;
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} while(counter > 0);
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extern void delay(int ticks);
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delay(ticks);
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#elif defined(CPU_PP) && defined(BOOTLOADER)
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unsigned stop = USEC_TIMER + ticks * (1000000/HZ);
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while (TIME_BEFORE(USEC_TIMER, stop))
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@ -24,7 +24,7 @@
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#include "timer.h"
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#include "thread.h"
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void tick_start(unsigned int interval_in_ms)
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static inline void tick_set(unsigned int interval_in_ms)
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{
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/*
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* Based on default PCLK of 49.1568MHz - scaling chosen to give
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@ -49,6 +49,12 @@ void tick_start(unsigned int interval_in_ms)
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TCON |= 1 << 21;
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/* reset manual bit */
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TCON &= ~(1 << 21);
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}
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void tick_start(unsigned int interval_in_ms)
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{
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tick_set(interval_in_ms);
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/* interval mode */
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TCON |= 1 << 22;
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/* start timer 4 */
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@ -58,6 +64,26 @@ void tick_start(unsigned int interval_in_ms)
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INTMSK &= ~TIMER4_MASK;
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}
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#ifdef BOOTLOADER
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void delay(int ticks)
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{
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volatile unsigned long counter;
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INTMSK |= TIMER4_MASK;
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tick_set(1000 * ticks / HZ);
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/* autoreload Off */
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TCON &= ~(1 << 22);
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/* start timer 4 */
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TCON |= (1 << 20);
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do {
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counter = TCNTO4;
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} while(counter > 0);
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}
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#endif /* BOOTLOADER */
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void TIMER4(void)
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{
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/* Run through the list of tick tasks */
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