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M:Robe 500 and TSC2100: Add more to the initialization. Some GPIO initializations are now removed - this will be hanled by the OF or bootloader (when loading from flash).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29220 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun 2011-02-06 19:33:40 +00:00
parent fafd50938c
commit 50c547c640
3 changed files with 29 additions and 20 deletions
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4
firmware/drivers/audio/tsc2100.c
View file

@ -117,7 +117,7 @@ void audiohw_close(void)
void audiohw_set_frequency(int fsel)
{
int reg_val;
reg_val = tsc2100_readreg(TSAC1_PAGE, TSAC1_ADDRESS);
reg_val = tsc2100_readreg(CONTROL_PAGE2, TSAC1_ADDRESS);
reg_val &= ~(0x07<<3);
@ -137,5 +137,5 @@ void audiohw_set_frequency(int fsel)
break;
}
tsc2100_writereg(TSAC1_PAGE, TSAC1_ADDRESS, reg_val);
tsc2100_writereg(CONTROL_PAGE2, TSAC1_ADDRESS, reg_val);
}

18
firmware/export/tsc2100.h
View file

@ -91,10 +91,6 @@ void tsc2100_keyclick(void);
#define VOLUME_MAX 0
#define VOLUME_MIN -630
/* ts audio control 1*/
#define TSAC1_PAGE 2
#define TSAC1_ADDRESS 0x00
/* ts audio control 2 */
#define TSAC2_PAGE 2
#define TSAC2_ADDRESS 0x04
@ -111,13 +107,13 @@ void tsc2100_keyclick(void);
#define TSAC2_DASTC (1<<1)
#define TSAC2_ADGAF (1<<0) /* r only */
/* ts codec power control */
#define TSCPC_PAGE 2
#define TSCPC_ADDRESS 0x05
/* ts audio control 3 */
#define TSAC3_PAGE 2
#define TSAC3_ADDRESS 0x06
#define CONTROL_PAGE2 2
#define TSAC1_ADDRESS 0x00 /* ts audio control 1*/
#define TSCSC_ADDRESS 0x03 /* Codec Sidetone Control */
#define TSCPC_ADDRESS 0x05 /* ts codec power control */
#define TSAC3_ADDRESS 0x06 /* ts audio control 3 */
#define TSPP1_ADDRESS 0x1b /* PLL Programability */
#define TSPP2_ADDRESS 0x1c /* PLL Programability */
/* ts audio control 4 */
#define TSAC4_PAGE 2

27
firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c
View file

@ -29,14 +29,19 @@
#include "dsp/ipc.h"
#include "mmu-arm.h"
/* These are global to save some latency when pcm_play_dma_get_peak_buffer is
/* This is global to save some latency when pcm_play_dma_get_peak_buffer is
* called.
*/
static void *start;
static size_t size;
void pcm_postinit(void)
{
/* Configure clock divider */
tsc2100_writereg(CONTROL_PAGE2, TSPP1_ADDRESS, 0x1120);
tsc2100_writereg(CONTROL_PAGE2, TSAC3_ADDRESS, 0x0800);
tsc2100_writereg(CONTROL_PAGE2, TSCPC_ADDRESS, 0x3B00);
tsc2100_writereg(CONTROL_PAGE2, TSAC1_ADDRESS, 0x0300);
tsc2100_writereg(CONTROL_PAGE2, TSCSC_ADDRESS, 0xC580);
audiohw_postinit();
}
@ -50,7 +55,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
{
int cnt = DSP_(_sdem_level);
unsigned long addr = (unsigned long) start +cnt;
unsigned long addr = (unsigned long) start + cnt;
*count = (cnt & 0xFFFFF) >> 1;
return (void *)((addr + 2) & ~3);
@ -58,16 +63,23 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
void pcm_play_dma_init(void)
{
IO_INTC_IRQ0 = 1 << 11;
IO_INTC_EINT0 |= 1 << 11;
IO_INTC_IRQ0 = INTR_IRQ0_IMGBUF;
bitset16(&IO_INTC_EINT0, INTR_EINT0_IMGBUF);
/* Set this as a FIQ */
IO_INTC_FISEL0 |= 1 << 11;
bitset16(&IO_INTC_FISEL0, INTR_EINT0_IMGBUF);
/* Enable the HPIB clock */
bitset16(&IO_CLK_MOD0, (CLK_MOD0_HPIB | CLK_MOD0_DSP));
IO_SDRAM_SDDMASEL = 0x24;
IO_DSPC_HPIB_CONTROL = 1 << 10 | 1 << 9 | 1 << 8 | 1 << 7 | 1 << 3 | 1 << 0;
dsp_reset();
dsp_load(dsp_image);
DSP_(_dma0_stopped)=1;
dsp_wake();
}
@ -133,8 +145,9 @@ void DSPHINT(void) __attribute__ ((section(".icode")));
void DSPHINT(void)
{
unsigned int i;
size_t size;
IO_INTC_FIQ0 = 1 << 11;
IO_INTC_FIQ0 = INTR_IRQ0_IMGBUF;
switch (dsp_message.msg)
{