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Gigabeat S: Move the LCD framebuffer address so that DRAM can be mapped flat between physical and virtual addresses. NO BOOTLOADER UPDATE SHOULD BE NEEDED. The firmware image now handles low-level system setup as well.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19935 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2009-02-07 10:09:13 +00:00
parent f747d9d39e
commit 4d3a020f27
6 changed files with 36 additions and 27 deletions
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9
bootloader/gigabeat-s.c
View file

@ -334,14 +334,17 @@ void main(void)
/* Flush and invalidate all caches (because vectors were written) */
invalidate_icache();
lcd_clear_display();
printf("Gigabeat S Rockbox Bootloader");
printf("Version %s", version);
system_init();
kernel_init();
enable_interrupt(IRQ_FIQ_STATUS);
lcd_init_device();
lcd_clear_display();
printf("Gigabeat S Rockbox Bootloader");
printf("Version %s", version);
/* Initialize KPP so we can poll the button states */
button_init_device();

11
firmware/export/imx31l.h
View file

@ -28,12 +28,14 @@
#define REG32_PTR_T volatile unsigned long *
/* Place in the section with the framebuffer */
#define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE)
#define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
#define TTB_SIZE (0x4000)
#define IRAM_SIZE (0x4000)
#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
#define FRAME ((void*)0x03f00000)
#define FRAME_SIZE (240*320*2)
/* Rockbox framebuffer address, not retail OS */
#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
#define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
#define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon))
/* USBOTG */
@ -411,6 +413,11 @@
#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
#define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
#define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
#define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
#define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
/* ATA */

3
firmware/target/arm/imx31/app.lds
View file

@ -34,7 +34,8 @@ STARTUP(target/arm/imx31/crt0.o)
MEMORY
{
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
DEVBSS : ORIGIN = 0x80100000 + FRAME_SIZE, LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE * 0x100000 - 0x100000), \
LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
}
SECTIONS

5
firmware/target/arm/imx31/boot.lds
View file

@ -8,7 +8,7 @@ STARTUP(target/arm/imx31/crt0.o)
#define DRAMSIZE (1 << 20) /* Limit 1 MB for bootloader */
#define DRAMORIG (0x02000000-0x00100000)
#define DRAMORIG 0x02000000
/* #define IRAMORIG 0x1FFFC000 */
#define IRAM DRAM
#define IRAMSIZE IRAM_SIZE
@ -19,7 +19,8 @@ STARTUP(target/arm/imx31/crt0.o)
MEMORY
{
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
DEVBSS : ORIGIN = 0x80100000 + FRAME_SIZE, LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE*0x100000 - 0x100000), \
LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
}
SECTIONS

25
firmware/target/arm/imx31/crt0.S
View file

@ -57,7 +57,6 @@ start:
newstart:
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
#ifdef BOOTLOADER
adr r2, remap_start /* Load PC-relative labels */
adr r3, remap_end
ldr r5, =TTB_BASE_ADDR /* TTB pointer */
@ -127,13 +126,6 @@ remap_start:
/*** End of L2 operations ***/
/* TTB Initialisation */
mov r2, r5
add r3, r5, #TTB_SIZE
mov r1, #0
1:
str r1, [r2], #4
cmp r2, r3
blo 1b
/* Set TTB base address */
mcr p15, 0, r5, c2, c0, 0
@ -157,32 +149,29 @@ remap_start:
add r1, r1, #(1 << 20) /* Next MB */
cmp r2, r3
blo 1b
sub r1, r1, #TTB_SIZE/4*(1 << 20) /* Back up */
bic r1, r1, #0x0ff00000 /* Back up */
/* Map 0x80000000 -> 0x0, cached */
mov r2, r5 /* TTB pointer */
add r3, r5, #63*4 /* End position */
add r3, r5, #64*4 /* End position */
orr r1, r1, #0x80000000 /* Physical address */
orr r1, r1, #((1 << 3) | /* cache flag */ \
(1 << 2)) /* buffer flag */
1:
str r1, [r2], #4
add r1, r1, #(1 << 20)
and r4, r1, #0x0ff00000
cmp r4, #0x00100000 /* Skip framebuffer */
addeq r1, r1, #(1 << 20)
cmp r2, r3
blo 1b
/* Map device section 0x80100000 to 0x03f00000 - buffered, not cached */
/* Map device section 0x83f00000 to 0x03f00000 - buffered, not cached */
bic r1, r1, #0x0ff00000
orr r1, r1, #0x00100000
orr r1, r1, #0x03f00000
bic r1, r1, #(1 << 3)
add r2, r5, #63*4
str r1, [r2]
/* Enable MMU */
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */
mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */
@ -230,8 +219,6 @@ L_post_remap:
.word remap_end
remap_end:
#endif /* BOOTLOADER */
#ifdef BOOTLOADER
/* Copy bootloader exception handler code to address 0 */
ldr r2, =_vectorsstart

10
firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c
View file

@ -27,6 +27,7 @@
#include "lcd-target.h"
#include "backlight-target.h"
#define MAIN_LCD_IDMAC_CHANNEL 14
#define LCDADDR(x, y) (&lcd_framebuffer[(y)][(x)])
static volatile bool lcd_on = true;
@ -46,6 +47,15 @@ extern void lcd_copy_buffer_rect(fb_data *dst, const fb_data *src,
/* LCD init */
void lcd_init_device(void)
{
/* Move the framebuffer */
#ifdef BOOTLOADER
/* Only do this once to avoid flicker */
memset(FRAME, 0x00, FRAME_SIZE);
#endif
IPU_IDMAC_CHA_EN &= ~(1ul << MAIN_LCD_IDMAC_CHANNEL);
IPU_IMA_ADDR = ((0x1 << 16) | (MAIN_LCD_IDMAC_CHANNEL << 4)) + (1 << 3);
IPU_IMA_DATA = FRAME_PHYS_ADDR;
IPU_IDMAC_CHA_EN |= (1ul << MAIN_LCD_IDMAC_CHANNEL);
}
/* Update a fraction of the display. */