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Fix RoLo on MIPS targets

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21185 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2009-06-04 11:57:43 +00:00
parent 398e1059c5
commit 48203093ce
2 changed files with 2 additions and 1 deletions
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2
firmware/rolo.c
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@ -181,7 +181,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
: : "r"(dest)
);
#elif defined(CPU_MIPS)
cpucache_invalidate();
__dcache_writeback_all();
asm volatile(
"jr %0 \n"
: : "r"(dest)

1
firmware/target/mips/mmu-mips.c
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@ -189,6 +189,7 @@ void __dcache_invalidate_all(void)
__CACHE_OP(DCIndexStTag, i);
}
void __dcache_writeback_all(void) __attribute__ ((section(".icode")));
void __dcache_writeback_all(void)
{
unsigned int i;