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rk27xx: substitute magic constants with meaningful names for clock gating

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Change-Id: I6c66c7496db3db78e5c959414464826134dbe200
This commit is contained in:
Marcin Bukat 2012-12-17 08:44:09 +01:00
parent 1fa406dc21
commit 2b6dfdb34e
9 changed files with 66 additions and 35 deletions
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32
firmware/export/rk27xx.h
View file

@ -124,6 +124,38 @@
#define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
#define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
#define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
#define CLKCFG_OTP (1<<0)
#define CLKCFG_DSP (1<<1)
#define CLKCFG_SDRAM (1<<2)
#define CLKCFG_HDMA (1<<3)
#define CLKCFG_DWDMA (1<<4)
#define CLKCFG_UHC (1<<5)
#define CLKCFG_UDC (1<<6)
/* 7 - 8 reserved */
#define CLKCFG_NAND (1<<9)
#define CLKCFG_A2A (1<<10)
#define CLKCFG_SRAM (1<<11)
#define CLKCFG_HCLK_LCDC (1<<12)
#define CLKCFG_LCDC (1<<13)
#define CLKCFG_HCLK_VIP (1<<14)
#define CLKCFG_VIP (1<<15)
#define CLKCFG_I2S (1<<16)
#define CLKCFG_PCLK_I2S (1<<17)
#define CLKCFG_UART0 (1<<18)
#define CLKCFG_UART1 (1<<19)
#define CLKCFG_I2C (1<<20)
#define CLKCFG_SPI (1<<21)
#define CLKCFG_SD (1<<22)
#define CLKCFG_PCLK_LSADC (1<<23)
#define CLKCFG_LSADC (1<<24)
#define CLKCFG_HCLK_HSADC (1<<25)
#define CLKCFG_HSADC (1<<26)
#define CLKCFG_GPIO (1<<27)
#define CLKCFG_TIMER (1<<28)
#define CLKCFG_PWM (1<<29)
#define CLKCFG_RTC (1<<30)
#define CLKCFG_WDT (1<<31)
#define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
#define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
#define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))

4
firmware/target/arm/rk27xx/adc-rk27xx.c
View file

@ -31,7 +31,7 @@ unsigned short adc_read(int channel)
unsigned short result;
/* ungate lsadc clocks */
SCU_CLKCFG &= ~(3<<23);
SCU_CLKCFG &= ~(CLKCFG_LSADC|CLKCFG_PCLK_LSADC);
/* wait a bit for clock to stabilize */
udelay(10);
@ -51,7 +51,7 @@ unsigned short adc_read(int channel)
result = (ADC_DATA & 0x3ff);
/* turn off lsadc clock when not in use */
SCU_CLKCFG |= (3<<23);
SCU_CLKCFG |= (CLKCFG_LSADC|CLKCFG_PCLK_LSADC);
return result;
}

4
firmware/target/arm/rk27xx/backlight-rk27xx.c
View file

@ -97,7 +97,7 @@ void _backlight_on(void)
lcd_enable(true);
#endif
/* enable PWM clock */
SCU_CLKCFG &= ~(1<<29);
SCU_CLKCFG &= ~CLKCFG_PWM;
/* set output pin as PWM pin */
SCU_IOMUXB_CON |= (1<<11); /* type<<11<<channel */
@ -115,7 +115,7 @@ void _backlight_off(void)
PWMT0_CTRL &= ~(1<<3) | (1<<0);
/* disable PWM clock */
SCU_CLKCFG |= (1<<29);
SCU_CLKCFG |= CLKCFG_PWM;
#ifdef HAVE_LCD_ENABLE
lcd_enable(false);
#endif

12
firmware/target/arm/rk27xx/i2c-rk27xx.c
View file

@ -123,7 +123,7 @@ void i2c_init(void)
/* ungate i2c module clock */
SCU_CLKCFG &= ~(1<< 20);
SCU_CLKCFG &= ~CLKCFG_I2C;
I2C_OPR |= (1<<7); /* reset state machine */
sleep(HZ/100);
@ -146,7 +146,7 @@ void i2c_init(void)
I2C_OPR |= (1<<6); /* enable i2c core */
/* turn off i2c module clock until we need to comunicate */
SCU_CLKCFG |= (1<< 20);
SCU_CLKCFG |= CLKCFG_I2C;
}
int i2c_write(unsigned char slave, int address, int len,
@ -159,7 +159,7 @@ int i2c_write(unsigned char slave, int address, int len,
i2c_iomux(slave);
/* ungate i2c clock */
SCU_CLKCFG &= ~(1<<20);
SCU_CLKCFG &= ~CLKCFG_I2C;
/* clear all flags */
I2C_ISR = 0x00;
@ -200,7 +200,7 @@ int i2c_write(unsigned char slave, int address, int len,
end:
mutex_unlock(&i2c_mtx);
SCU_CLKCFG |= (1<<20);
SCU_CLKCFG |= CLKCFG_I2C;
return ret;
}
@ -213,7 +213,7 @@ int i2c_read(unsigned char slave, int address, int len, unsigned char *data)
i2c_iomux(slave);
/* ungate i2c module clock */
SCU_CLKCFG &= ~(1<<20);
SCU_CLKCFG &= ~CLKCFG_I2C;
/* clear all flags */
I2C_ISR = 0x00;
@ -270,6 +270,6 @@ int i2c_read(unsigned char slave, int address, int len, unsigned char *data)
end:
mutex_unlock(&i2c_mtx);
SCU_CLKCFG |= (1<<20);
SCU_CLKCFG |= CLKCFG_I2C;
return ret;
}

2
firmware/target/arm/rk27xx/kernel-rk27xx.c
View file

@ -39,7 +39,7 @@ void tick_start(unsigned int interval_in_ms)
unsigned int cycles = 50000 * interval_in_ms;
/* enable timer clock */
SCU_CLKCFG &= ~(1<<28);
SCU_CLKCFG &= ~CLKCFG_TIMER;
/* configure timer0 */
TMR0LR = cycles;

9
firmware/target/arm/rk27xx/pcm-rk27xx.c
View file

@ -61,7 +61,7 @@ void pcm_play_dma_stop(void)
static void hdma_i2s_transfer(const void *addr, size_t size)
{
SCU_CLKCFG &= ~(1<<3); /* enable HDMA clock */
SCU_CLKCFG &= ~CLKCFG_HDMA; /* enable HDMA clock */
commit_discard_dcache_range(addr, size);
@ -117,12 +117,12 @@ void pcm_play_dma_pause(bool pause)
{
if(pause)
{
SCU_CLKCFG |= (1<<3);
SCU_CLKCFG |= CLKCFG_HDMA;
locked = 1;
}
else
{
SCU_CLKCFG &= ~(1<<3);
SCU_CLKCFG &= ~CLKCFG_HDMA;
locked = 0;
}
}
@ -148,8 +148,7 @@ static void i2s_init(void)
#endif
/* enable i2s clocks */
SCU_CLKCFG &= ~((1<<17) | /* i2s_pclk */
(1<<16)); /* i2s_clk */
SCU_CLKCFG &= ~(CLKCFG_PCLK_I2S | CLKCFG_I2S);
/* configure I2S module */
I2S_IER = 0; /* disable all i2s interrupts */

6
firmware/target/arm/rk27xx/sd-rk27xx.c
View file

@ -401,7 +401,7 @@ static void init_controller(void)
SCU_IOMUXA_CON |= IOMUX_SD;
/* enable and unmask SD interrupts in interrupt controller */
SCU_CLKCFG &= ~(1<<22);
SCU_CLKCFG &= ~CLKCFG_SD;
INTC_IMR |= (1<<10);
INTC_IECR |= (1<<10);
@ -729,12 +729,12 @@ void sd_enable(bool on)
/* enable or disable clock signal for SD module */
if (on)
{
SCU_CLKCFG &= ~(1<<22);
SCU_CLKCFG &= ~CLKCFG_SD;
led(true);
}
else
{
SCU_CLKCFG |= (1<<22);
SCU_CLKCFG |= CLKCFG_SD;
led(false);
}
}

30
firmware/target/arm/rk27xx/system-rk27xx.c
View file

@ -130,20 +130,20 @@ void system_init(void)
MCSDR_T_RCD = 1; /* active to RD/WR delay */
/* turn off clock for unused modules */
SCU_CLKCFG |= (1<<31) | /* WDT pclk */
(1<<30) | /* RTC pclk */
(1<<26) | /* HS_ADC clock */
(1<<25) | /* HS_ADC HCLK */
(1<<21) | /* SPI clock */
(1<<19) | /* UART1 clock */
(1<<18) | /* UART0 clock */
(1<<15) | /* VIP clock */
(1<<14) | /* VIP HCLK */
(1<<13) | /* LCDC clock */
(1<<9) | /* NAND HCLK */
(1<<5) | /* USB host HCLK */
(1<<1) | /* DSP clock */
(1<<0); /* OTP clock (dunno what it is */
SCU_CLKCFG |= CLKCFG_WDT | /* WDT pclk */
CLKCFG_RTC | /* RTC pclk */
CLKCFG_HSADC | /* HS_ADC clock */
CLKCFG_HCLK_HSADC | /* HS_ADC HCLK */
CLKCFG_SPI | /* SPI clock */
CLKCFG_UART1 | /* UART1 clock */
CLKCFG_UART0 | /* UART0 clock */
CLKCFG_VIP | /* VIP clock */
CLKCFG_HCLK_VIP | /* VIP HCLK */
CLKCFG_LCDC | /* LCDC clock */
CLKCFG_NAND | /* NAND HCLK */
CLKCFG_UHC | /* USB host HCLK */
CLKCFG_DSP | /* DSP clock */
CLKCFG_OTP; /* OTP clock (dunno what it is */
/* turn off DSP pll */
SCU_PLLCON2 |= (1<<22);
@ -157,7 +157,7 @@ void system_init(void)
void system_reboot(void)
{
/* use Watchdog to reset */
SCU_CLKCFG &= ~(1<<31);
SCU_CLKCFG &= ~CLKCFG_WDT;
WDTLR = 1;
WDTCON = (1<<4) | (1<<3);

2
firmware/target/arm/rk27xx/usb-drv-rk27xx.c
View file

@ -642,7 +642,7 @@ void usb_drv_init(void)
int ep_num;
/* enable USB clock */
SCU_CLKCFG &= ~(1<<6);
SCU_CLKCFG &= ~CLKCFG_UDC;
/* 1. do soft disconnect */
DEV_CTL = DEV_SELF_PWR;