x1000: Centralize common definitions, memory layout
Change-Id: I8daad058ae55d4b750b1ae407153e4917de5d095
This commit is contained in:
Aidan MacDonald
parent
ed8c977e2f
commit
20fc928221
7 changed files with 103 additions and 56 deletions
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@ -77,9 +77,9 @@ OUTPUT_FORMAT(elf32-littlemips)
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#include "cpu.h"
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - FRAME_SIZE - TTB_SIZE)
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#elif CONFIG_CPU==X1000
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#include "config.h"
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#include "cpu.h"
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#undef STUBOFFSET
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#define STUBOFFSET 0x4000
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#define DRAMSIZE (X1000_DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
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#endif
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/* default to full RAM (minus codecs&plugins) unless specified otherwise */
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@ -179,7 +179,7 @@ OUTPUT_FORMAT(elf32-littlemips)
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/* The bit of IRAM that is available is used in the core */
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#elif CONFIG_CPU == X1000
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#define DRAMORIG (0x80000000 + STUBOFFSET)
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#define DRAMORIG X1000_DRAM_BASE
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#define IRAM DRAM
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#define IRAMSIZE 0
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@ -77,3 +77,6 @@
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#if CONFIG_CPU == RK27XX
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#include "rk27xx.h"
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#endif
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#if CONFIG_CPU == X1000
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#include "x1000.h"
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#endif
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72
firmware/export/x1000.h
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72
firmware/export/x1000.h
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@ -0,0 +1,72 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __X1000_H__
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#define __X1000_H__
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#include "config.h"
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/* Frequency of external oscillator EXCLK */
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//#define X1000_EXCLK_FREQ 24000000
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/* Maximum CPU frequency that can be achieved on the target */
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//#define CPU_FREQ 1008000000
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/* Only 24 MHz and 26 MHz external oscillators are supported by the X1000 */
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#if X1000_EXCLK_FREQ == 24000000
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# define X1000_EXCLK_24MHZ
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#elif X1000_EXCLK_FREQ == 26000000
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# define X1000_EXCLK_26MHZ
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#else
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# error "Unsupported EXCLK freq"
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#endif
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/* On-chip TCSM (tightly coupled shared memory), aka IRAM */
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#define X1000_TCSM_BASE 0xf4000000
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#define X1000_TCSM_SIZE (16 * 1024)
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/* External SDRAM */
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#define X1000_SDRAM_BASE 0x80000000
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#define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024)
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/* Memory definitions for Rockbox */
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#define X1000_IRAM_BASE X1000_SDRAM_BASE
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#define X1000_IRAM_SIZE (16 * 1024)
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#define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE)
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#define X1000_DRAM_BASE X1000_IRAM_END
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#define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE)
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#define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE)
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#define X1000_STACKSIZE 0x1e00
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#define X1000_IRQSTACKSIZE 0x300
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/* Convert kseg0 address to physical address or uncached address */
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#define PHYSADDR(x) ((unsigned long)(x) & 0x1fffffff)
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#define UNCACHEDADDR(x) (PHYSADDR(x) | 0xa0000000)
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/* Defines for usb-designware driver */
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#define OTGBASE 0xb3500000
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#define USB_NUM_ENDPOINTS 9
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/* CPU cache parameters */
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#define CACHEALIGN_BITS 5
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#define CACHE_SIZE (16 * 1024)
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#endif /* __X1000_H__ */
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@ -1,30 +1,21 @@
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#include "config.h"
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#include "cpu.h"
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OUTPUT_FORMAT("elf32-littlemips")
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OUTPUT_ARCH(MIPS)
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ENTRY(_start)
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STARTUP(target/mips/ingenic_x1000/crt0.o)
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/* Stub area is used for loading new firmware via RoLo */
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#define STUBSIZE 0x4000
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#define SDRAM_ORIG 0x80000000
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/* IRAM contains stub, DRAM contains main app */
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#define IRAMORIG SDRAM_ORIG
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#define IRAMSIZE STUBSIZE
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#define DRAMORIG (SDRAM_ORIG + STUBSIZE)
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#define DRAMSIZE (MEMORYSIZE * 0x100000 - STUBSIZE)
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/* End of the audio buffer, where the codec buffer starts */
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#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
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#define ENDAUDIOADDR (X1000_DRAM_END - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
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/* Where the codec buffer ends, and the plugin buffer starts */
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#define ENDCODECADDR (ENDAUDIOADDR + CODEC_SIZE)
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MEMORY
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{
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = X1000_IRAM_BASE, LENGTH = X1000_IRAM_SIZE
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DRAM : ORIGIN = X1000_DRAM_BASE, LENGTH = X1000_DRAM_SIZE
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}
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SECTIONS
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@ -50,7 +41,7 @@ SECTIONS
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*(.sdata*);
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} > DRAM
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.iram IRAMORIG: AT (_bssbegin)
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.iram X1000_IRAM_BASE: AT (_bssbegin)
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{
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_iramstart = .;
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. = 0x000; /* TLB refill */
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@ -75,10 +66,10 @@ SECTIONS
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{
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*(.stack);
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stackbegin = .;
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. += 0x1E00;
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. += X1000_STACKSIZE;
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stackend = .;
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_irqstackbegin = .;
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. += 0x300;
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. += X1000_IRQSTACKSIZE;
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_irqstackend = .;
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} > IRAM
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@ -93,23 +84,17 @@ SECTIONS
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_end = .;
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} > DRAM
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#ifdef BOOTLOADER
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. = ALIGN(4);
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loadbuffer = .;
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. += 0x100000 * 4; /* Allow 4 MiB for the rockbox binary */
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loadbufferend = .;
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#else
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.audiobuf :
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{
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. = ALIGN(4); /* XXX might need more alignment here */
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. = ALIGN(4);
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audiobuffer = .;
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loadbuffer = .;
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} > DRAM
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loadbufferend = ENDAUDIOADDR;
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audiobufend = ENDAUDIOADDR;
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codecbuf = ENDAUDIOADDR;
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pluginbuf = ENDCODECADDR;
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#endif
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/DISCARD/ :
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{
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@ -56,8 +56,8 @@ const struct spl_boot_option spl_boot_options[] = {
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*/
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.nand_addr = 0x6800,
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.nand_size = 0x19800,
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.load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */
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.exec_addr = 0x80004000,
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.load_addr = X1000_DRAM_BASE - 8, /* first 8 bytes are bootloader ID */
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.exec_addr = X1000_DRAM_BASE,
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.cmdline = NULL,
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},
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{
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@ -1,23 +1,22 @@
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#include "config.h"
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#include "cpu.h"
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OUTPUT_FORMAT("elf32-littlemips")
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OUTPUT_ARCH(MIPS)
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ENTRY(_start)
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STARTUP(target/mips/ingenic_x1000/crt0.o)
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#define DRAMORIG 0x80000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000)
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#define USED_DRAM 16K
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/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
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*
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* The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
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* The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
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* The maskrom will jump to that address (via jalr) after loading the SPL.
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*/
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MEMORY {
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TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800
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DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM
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/* First 4k of TCSM is used by mask ROM for stack + variables,
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* and the next 2k are occupied by SPL header */
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TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800,
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LENGTH = X1000_TCSM_SIZE - 0x1800
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/* Small area of DRAM is required for NAND bounce buffers,
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* though not strictly necessary as ECC isn't really practical
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* this early in the boot */
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DRAM : ORIGIN = X1000_DRAM_END - 16K,
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LENGTH = 16K
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}
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SECTIONS
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@ -22,35 +22,23 @@
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#ifndef __SYSTEM_TARGET_H__
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#define __SYSTEM_TARGET_H__
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/* For the sake of system.h CACHEALIGN macros.
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* We need this to align DMA buffers, etc.
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*/
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#define CACHEALIGN_BITS 5
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#define CACHE_SIZE (16*1024)
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#ifdef DEBUG
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/* Define this to get CPU idle stats, visible in the debug menu. */
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# define X1000_CPUIDLE_STATS
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#endif
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#define OTGBASE 0xb3500000
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#define USB_NUM_ENDPOINTS 9
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#include "cpu.h"
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#include "mmu-mips.h"
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#include "mipsregs.h"
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#include "mipsr2-endian.h"
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#include <stdint.h>
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/* Get physical address for DMA */
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#define PHYSADDR(addr) (((unsigned long)(addr)) & 0x1fffffff)
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#define HIGHEST_IRQ_LEVEL 0
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/* Rockbox API */
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#define enable_irq() set_c0_status(ST0_IE)
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#define disable_irq() clear_c0_status(ST0_IE)
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#define disable_irq_save() set_irq_level(0)
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#define restore_irq(arg) write_c0_status(arg)
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#define HIGHEST_IRQ_LEVEL 0
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static inline int set_irq_level(int lev)
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{
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