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The GPIO registers are 8-bit, so define them as such.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18835 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman 2008-10-19 12:47:58 +00:00
parent 2f50cd58b9
commit 14ee31865e
1 changed files with 8 additions and 8 deletions
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16
firmware/export/as3525.h
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@ -296,20 +296,20 @@ interface */
/* GPIO registers */
#define GPIOA_DIR (*(volatile unsigned long*)(GPIOA_BASE+0x400))
#define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400))
#define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420))
#define GPIOA_PIN(a) (*(volatile unsigned long*)(GPIOA_BASE+4*(1<<(a))))
#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+4*(1<<(a))))
#define GPIOB_DIR (*(volatile unsigned long*)(GPIOB_BASE+0x400))
#define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400))
#define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420))
#define GPIOB_PIN(a) (*(volatile unsigned long*)(GPIOB_BASE+4*(1<<(a))))
#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+4*(1<<(a))))
#define GPIOC_DIR (*(volatile unsigned long*)(GPIOC_BASE+0x400))
#define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400))
#define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420))
#define GPIOC_PIN(a) (*(volatile unsigned long*)(GPIOC_BASE+4*(1<<(a))))
#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+4*(1<<(a))))
#define GPIOD_DIR (*(volatile unsigned long*)(GPIOD_BASE+0x400))
#define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400))
#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
#define GPIOD_PIN(a) (*(volatile unsigned long*)(GPIOD_BASE+4*(1<<(a))))
#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a))))
#endif /*__AS3525_H__*/