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CONFIG_USBOTG fixes

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12377 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jonathan Gordon 2007-02-18 01:17:06 +00:00
parent c2f05592ee
commit 1083de8e7d
3 changed files with 8 additions and 8 deletions
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8
apps/main.c
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@ -95,11 +95,11 @@
#include "lcd-remote.h"
#endif
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
#include "isp1362.h"
#endif
#if CONFIG_USBOTG == USBOTG_M5636
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_M5636
#include "m5636.h"
#endif
@ -350,9 +350,9 @@ static void init(void)
adc_init();
usb_init();
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
isp1362_init();
#elif CONFIG_USBOTG == USBOTG_M5636
#elif defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_M5636
m5636_init();
#endif

2
firmware/target/coldfire/crt0.S
View file

@ -78,7 +78,7 @@ start:
move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire
* IDE interface logic. */
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
/* Chip select 3 - USBOTG controller */
move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
move.l %d0,(0x0a4,%a0)

6
firmware/target/coldfire/iriver/system-iriver.c
View file

@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00001580; /* LCD: 5 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x038be025 | (PLLCR & 0x70400000);
CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x00800200 | (PLLCR & 0x70400000);
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
#endif
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */