Improve motion compensation for ARM: * Use less registers in the simple copy routines -> less stack usage. * Save a few instructions in constants + jumptable handling. * ARM6 optimisations. Unfortunately we can't just use uhadd8 because that rounds down, while we have to round up.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25776 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
f2759305a9
commit
0fd111d431
1 changed files with 180 additions and 162 deletions
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@ -20,6 +20,8 @@
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@
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@ $Id$
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#include "config.h" /* Rockbox: ARM architecture version */
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.text
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@ ----------------------------------------------------------------
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@ -28,11 +30,14 @@
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MC_put_o_16:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r11, lr} @ R14 is also called LR
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stmfd sp!, {r4-r7, lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_o_16_align_jt
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add r5, r5, r4, lsl #2
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ldr pc, [r5]
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ldr pc, [pc, r4, lsl #2]
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.word 0
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.word MC_put_o_16_align0
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.word MC_put_o_16_align1
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.word MC_put_o_16_align2
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.word MC_put_o_16_align3
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MC_put_o_16_align0:
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ldmia r1, {r4-r7}
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@ -42,128 +47,7 @@ MC_put_o_16_align0:
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_o_16_align0
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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.macro PROC shift
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ldmia r1, {r4-r8}
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add r1, r1, r2
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mov r9, r4, lsr #(\shift)
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@@ pld [r1]
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mov r10, r5, lsr #(\shift)
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orr r9, r9, r5, lsl #(32-\shift)
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mov r11, r6, lsr #(\shift)
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orr r10, r10, r6, lsl #(32-\shift)
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mov r12, r7, lsr #(\shift)
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orr r11, r11, r7, lsl #(32-\shift)
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orr r12, r12, r8, lsl #(32-\shift)
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stmia r0, {r9-r12}
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subs r3, r3, #1
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add r0, r0, r2
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.endm
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MC_put_o_16_align1:
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and r1, r1, #0xFFFFFFFC
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1: PROC(8)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_align2:
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and r1, r1, #0xFFFFFFFC
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1: PROC(16)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_align3:
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and r1, r1, #0xFFFFFFFC
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1: PROC(24)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_align_jt:
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.word MC_put_o_16_align0
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.word MC_put_o_16_align1
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.word MC_put_o_16_align2
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.word MC_put_o_16_align3
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@ ----------------------------------------------------------------
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.align
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.global MC_put_o_8
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MC_put_o_8:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r10, lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_o_8_align_jt
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add r5, r5, r4, lsl #2
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ldr pc, [r5]
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MC_put_o_8_align0:
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ldmia r1, {r4-r5}
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add r1, r1, r2
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@@ pld [r1]
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stmia r0, {r4-r5}
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add r0, r0, r2
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subs r3, r3, #1
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bne MC_put_o_8_align0
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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.macro PROC8 shift
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ldmia r1, {r4-r6}
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add r1, r1, r2
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mov r9, r4, lsr #(\shift)
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@@ pld [r1]
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mov r10, r5, lsr #(\shift)
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orr r9, r9, r5, lsl #(32-\shift)
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orr r10, r10, r6, lsl #(32-\shift)
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stmia r0, {r9-r10}
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subs r3, r3, #1
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add r0, r0, r2
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.endm
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MC_put_o_8_align1:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(8)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_align2:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(16)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_align3:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(24)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_align_jt:
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.word MC_put_o_8_align0
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.word MC_put_o_8_align1
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.word MC_put_o_8_align2
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.word MC_put_o_8_align3
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@ ----------------------------------------------------------------
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.macro AVG_PW rW1, rW2
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mov \rW2, \rW2, lsl #24
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orr \rW2, \rW2, \rW1, lsr #8
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eor r9, \rW1, \rW2
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and \rW2, \rW1, \rW2
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and r10, r9, r12
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add \rW2, \rW2, r10, lsr #1
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and r10, r9, r11
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add \rW2, \rW2, r10
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.endm
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.align
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.global MC_put_x_16
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MC_put_x_16:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_x_16_align_jt
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ldr r11, [r5]
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mvn r12, r11
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add r5, r5, r4, lsl #2
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ldr pc, [r5, #4]
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ldmfd sp!, {r4-r7, pc} @@ update PC with LR content.
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.macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
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mov \R0, \R0, lsr #(\shift)
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@ -175,9 +59,153 @@ MC_put_x_16:
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mov \R3, \R3, lsr #(\shift)
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orr \R3, \R3, \R4, lsl #(32 - \shift)
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mov \R4, \R4, lsr #(\shift)
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@ and \R4, \R4, #0xFF
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.endm
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MC_put_o_16_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r7, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_QW 8, r4, r5, r6, r7, r12
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stmia r0, {r4-r7}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r7, pc} @@ update PC with LR content.
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MC_put_o_16_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r7, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_QW 16, r4, r5, r6, r7, r12
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stmia r0, {r4-r7}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r7, pc} @@ update PC with LR content.
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MC_put_o_16_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r7, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_QW 24, r4, r5, r6, r7, r12
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stmia r0, {r4-r7}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r7, pc} @@ update PC with LR content.
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@ ----------------------------------------------------------------
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.align
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.global MC_put_o_8
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MC_put_o_8:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4, r5, lr} @ R14 is also called LR
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and r4, r1, #3
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ldr pc, [pc, r4, lsl #2]
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.word 0
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.word MC_put_o_8_align0
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.word MC_put_o_8_align1
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.word MC_put_o_8_align2
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.word MC_put_o_8_align3
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MC_put_o_8_align0:
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ldmia r1, {r4, r5}
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add r1, r1, r2
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@@ pld [r1]
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stmia r0, {r4, r5}
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add r0, r0, r2
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subs r3, r3, #1
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bne MC_put_o_8_align0
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ldmfd sp!, {r4, r5, pc} @@ update PC with LR content.
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.macro ADJ_ALIGN_DW shift, R0, R1, R2
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mov \R0, \R0, lsr #(\shift)
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orr \R0, \R0, \R1, lsl #(32 - \shift)
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mov \R1, \R1, lsr #(\shift)
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orr \R1, \R1, \R2, lsl #(32 - \shift)
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mov \R2, \R2, lsr #(\shift)
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.endm
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MC_put_o_8_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4, r5, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 8, r4, r5, r12
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stmia r0, {r4, r5}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4, r5, pc} @@ update PC with LR content.
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MC_put_o_8_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4, r5, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 16, r4, r5, r12
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stmia r0, {r4, r5}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4, r5, pc} @@ update PC with LR content.
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MC_put_o_8_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4, r5, r12}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 24, r4, r5, r12
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stmia r0, {r4, r5}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4, r5, pc} @@ update PC with LR content.
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@ ----------------------------------------------------------------
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.macro AVG_PW rW1, rW2
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mov \rW2, \rW2, lsl #24
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orr \rW2, \rW2, \rW1, lsr #8
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eor r9, \rW1, \rW2
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#if ARM_ARCH >= 6
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uhadd8 \rW2, \rW1, \rW2
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#else
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and \rW2, \rW1, \rW2
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and r10, r9, r11
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add \rW2, \rW2, r10, lsr #1
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#endif
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and r9, r9, r12
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add \rW2, \rW2, r9
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.endm
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#if ARM_ARCH >= 6
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#define HIGH_REGS r9
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#else
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#define HIGH_REGS r9-r11
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#endif
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.align
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.global MC_put_x_16
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MC_put_x_16:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r8, HIGH_REGS, lr} @ R14 is also called LR
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and r4, r1, #3
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ldr r12, 2f
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#if ARM_ARCH < 6
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mvn r11, r12
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#endif
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ldr pc, [pc, r4, lsl #2]
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2: .word 0x01010101
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.word MC_put_x_16_align0
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.word MC_put_x_16_align1
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.word MC_put_x_16_align2
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.word MC_put_x_16_align3
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MC_put_x_16_align0:
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ldmia r1, {r4-r8}
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add r1, r1, r2
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@ -190,7 +218,8 @@ MC_put_x_16_align0:
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_16_align0
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content.
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MC_put_x_16_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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@ -205,7 +234,8 @@ MC_put_x_16_align1:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content.
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MC_put_x_16_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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@ -220,7 +250,8 @@ MC_put_x_16_align2:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content.
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MC_put_x_16_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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@ -235,13 +266,7 @@ MC_put_x_16_align3:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_16_align_jt:
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.word 0x01010101
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.word MC_put_x_16_align0
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.word MC_put_x_16_align1
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.word MC_put_x_16_align2
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.word MC_put_x_16_align3
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ldmfd sp!, {r4-r8, HIGH_REGS, pc} @@ update PC with LR content.
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@ ----------------------------------------------------------------
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.align
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@ -249,22 +274,18 @@ MC_put_x_16_align_jt:
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MC_put_x_8:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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stmfd sp!, {r4-r6, HIGH_REGS, lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_x_8_align_jt
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ldr r11, [r5]
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mvn r12, r11
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add r5, r5, r4, lsl #2
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ldr pc, [r5, #4]
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.macro ADJ_ALIGN_DW shift, R0, R1, R2
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mov \R0, \R0, lsr #(\shift)
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orr \R0, \R0, \R1, lsl #(32 - \shift)
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mov \R1, \R1, lsr #(\shift)
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orr \R1, \R1, \R2, lsl #(32 - \shift)
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mov \R2, \R2, lsr #(\shift)
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@ and \R4, \R4, #0xFF
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.endm
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ldr r12, 2f
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#if ARM_ARCH < 6
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mvn r11, r12
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#endif
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ldr pc, [pc, r4, lsl #2]
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2: .word 0x01010101
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.word MC_put_x_8_align0
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.word MC_put_x_8_align1
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.word MC_put_x_8_align2
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.word MC_put_x_8_align3
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MC_put_x_8_align0:
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ldmia r1, {r4-r6}
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@ -276,7 +297,8 @@ MC_put_x_8_align0:
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_8_align0
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content.
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MC_put_x_8_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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||||
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|
@ -289,7 +311,8 @@ MC_put_x_8_align1:
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subs r3, r3, #1
|
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add r0, r0, r2
|
||||
bne 1b
|
||||
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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||||
ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content.
|
||||
|
||||
MC_put_x_8_align2:
|
||||
and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
|
||||
|
|
@ -302,7 +325,8 @@ MC_put_x_8_align2:
|
|||
subs r3, r3, #1
|
||||
add r0, r0, r2
|
||||
bne 1b
|
||||
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
|
||||
ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content.
|
||||
|
||||
MC_put_x_8_align3:
|
||||
and r1, r1, #0xFFFFFFFC
|
||||
1: ldmia r1, {r4-r6}
|
||||
|
|
@ -315,10 +339,4 @@ MC_put_x_8_align3:
|
|||
subs r3, r3, #1
|
||||
add r0, r0, r2
|
||||
bne 1b
|
||||
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
|
||||
MC_put_x_8_align_jt:
|
||||
.word 0x01010101
|
||||
.word MC_put_x_8_align0
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.word MC_put_x_8_align1
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||||
.word MC_put_x_8_align2
|
||||
.word MC_put_x_8_align3
|
||||
ldmfd sp!, {r4-r6, HIGH_REGS, pc} @@ update PC with LR content.
|
||||
|
|
|
|||
Loading…
Reference in a new issue