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Some small cleanups and code for testing

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15312 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun 2007-10-26 05:17:15 +00:00
parent cf86a9886f
commit 0a632680e9
5 changed files with 77 additions and 34 deletions
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5
bootloader/mrobe500.c
View file

@ -42,6 +42,7 @@
#include "uart-target.h"
#include "tsc2100.h"
#include "time.h"
#include "system-arm.h"
#define MRDEBUG
@ -168,6 +169,10 @@ void main(void)
lcd_init();
system_init();
kernel_init();
set_irq_level(0);
set_fiq_status(FIQ_ENABLED);
adc_init();
button_init();
backlight_init();

2
firmware/export/dm320.h
View file

@ -24,7 +24,7 @@
#ifndef __DM320_H__
#define __DM320_H__
#define LCD_BUFFER_SIZE (640*480*4)
#define LCD_BUFFER_SIZE (640*480*2)
#define TTB_SIZE (0x4000)
/* must be 16Kb (0x4000) aligned */
#define TTB_BASE ((unsigned int *)(0x04900000 - TTB_SIZE)) /* End of memory */

2
firmware/target/arm/crt0.S
View file

@ -42,7 +42,7 @@ newstart:
msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
#endif
#if !defined(BOOTLOADER) || (CONFIG_CPU == DM320)
#if !defined(BOOTLOADER)
#if !defined(DEBUG)
/* Copy exception handler code to address 0 */
ldr r2, =_vectorsstart

80
firmware/target/arm/tms320dm320/crt0.S
View file

@ -28,9 +28,22 @@
.global start
start:
msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
.equ INTC_IRQ0, 0x00030508
.equ INTC_IRQ1, 0x0003050A
.equ INTC_IRQ2, 0x0003050C
.equ INTC_FIQ0, 0x00030500
.equ INTC_FIQ1, 0x00030502
.equ INTC_FIQ2, 0x00030504
.equ INTC_EINT0, 0x00030528
.equ INTC_EINT1, 0x0003052A
.equ INTC_EINT2, 0x0003052C
.equ INTC_FISEL0, 0x00030520
.equ INTC_FISEL1, 0x00030522
.equ INTC_FISEL2, 0x00030524
.equ INTC_MASK, 0xFFFFFFFF
msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
#if !defined(DEBUG)
/* Copy exception handler code to address 0 */
ldr r2, =_vectorsstart
ldr r3, =_vectorsend
@ -40,13 +53,6 @@ start:
ldrhi r5, [r4], #4
strhi r5, [r2], #4
bhi 1b
#else
ldr r1, =vectors
ldr r0, =irq_handler
str r0, [r1, #24]
ldr r0, =fiq_handler
str r0, [r1, #28]
#endif
/* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
mrc p15, 0, r0, c1, c0, 0
@ -58,9 +64,38 @@ start:
orr r0, r0, #0x00000002
mcr p15, 0, r0, c1, c0, 0
#if !defined(BOOTLOADER)
#if 0
/* mask interrupts */
ldr r1, =INTC_MASK
ldr r2, =INTC_IRQ0
strh r1, [r2]
ldr r2, =INTC_IRQ1
strh r1, [r2]
ldr r2, =INTC_IRQ2
strh r1, [r2]
ldr r2, =INTC_FIQ0
strh r1, [r2]
ldr r2, =INTC_FIQ1
strh r1, [r2]
ldr r2, =INTC_FIQ2
strh r1, [r2]
#if !defined(STUB)
mov r1, #0
ldr r2, =INTC_EINT0
strh r1, [r2]
ldr r2, =INTC_EINT1
strh r1, [r2]
ldr r2, =INTC_EINT2
strh r1, [r2]
ldr r2, =INTC_FISEL0
strh r1, [r2]
ldr r2, =INTC_FISEL1
strh r1, [r2]
ldr r2, =INTC_FISEL2
strh r1, [r2]
#endif
#if !defined(BOOTLOADER) && !defined(STUB)
/* Zero out IBSS */
ldr r2, =_iedata
ldr r3, =_iend
@ -79,8 +114,7 @@ start:
ldrhi r5, [r2], #4
strhi r5, [r3], #4
bhi 1b
#endif /* !STUB */
#endif /* !BOOTLOADER */
#endif /* !BOOTLOADER,!STUB */
/* Initialise bss section to zero */
ldr r2, =_edata
@ -91,27 +125,30 @@ start:
strhi r4, [r2], #4
bhi 1b
/* Set up some stack and munge it with 0xdeadbeef */
ldr r3, =stackend
ldr r2, =stackbegin
/* Load stack munge value */
ldr r4, =0xdeadbeef
/* Set up some stack and munge it with 0xdeadbeef */
ldr r2, =stackbegin
ldr r3, =stackend
1:
cmp r3, r2
strhi r4, [r2], #4
bhi 1b
/* Set up stack for IRQ mode */
msr cpsr_c, #0xd2
msr cpsr_c, #0x92 /* IRQ disabled, FIQ enabled */
ldr sp, =irq_stack
/* Set up stack for FIQ mode */
msr cpsr_c, #0xd1
msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */
ldr sp, =fiq_stack
/* Let abort and undefined modes use IRQ stack */
msr cpsr_c, #0xd7
msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */
ldr sp, =irq_stack
msr cpsr_c, #0xdb
msr cpsr_c, #0xdb /* IRQ/FIQ disabled */
ldr sp, =irq_stack
/* Switch to supervisor mode (no IRQ) */
msr cpsr_c, #0xd3
ldr sp, =stackend
@ -203,6 +240,9 @@ UIE:
b UIE
#endif
/* Align stacks to cache line boundary */
.balign 16
/* 256 words of IRQ stack */
.space 256*4
irq_stack:

18
firmware/target/arm/tms320dm320/system-dm320.c
View file

@ -22,6 +22,7 @@
#include "system.h"
#include "panic.h"
#include "uart-target.h"
#include "system-arm.h"
#include "spi.h"
#define default_interrupt(name) \
@ -143,11 +144,6 @@ void system_reboot(void)
}
void enable_interrupts (void)
{
asm volatile ("msr cpsr_c, #0x13" );
}
void system_init(void)
{
/* taken from linux/arch/arm/mach-itdm320-20/irq.c */
@ -171,22 +167,24 @@ void system_init(void)
IO_INTC_FISEL1 = 0;
IO_INTC_FISEL2 = 0;
IO_INTC_ENTRY_TBA0 =
IO_INTC_ENTRY_TBA0 = 0;
IO_INTC_ENTRY_TBA1 = 0;
/* set GIO26 (reset pin) to output and low */
IO_GIO_BITCLR1=(1<<10);
IO_GIO_DIR1&=~(1<<10);
enable_interrupts();
uart_init();
spi_init();
/* MMU initialization (Starts data and instruction cache) */
ttb_init();
map_section(0, 0, 0x1000, CACHE_NONE); /* Make sure everything is mapped on itself */
map_section(0x00900000, 0x00900000, 64, CACHE_ALL); /* Enable caching for RAM */
map_section((int)FRAME, (int)FRAME, 2, BUFFERED); /* enable buffered writing for the framebuffer */
/* Make sure everything is mapped on itself */
map_section(0, 0, 0x1000, CACHE_NONE);
/* Enable caching for RAM */
map_section(0x00900000, 0x00900000, 64, CACHE_ALL);
/* enable buffered writing for the framebuffer */
map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
enable_mmu();
}