APE: Fused vector math for the filters on ARMv5te. Speedup on Cowon D2 is ~4% for -c2000..-c4000 (less for -c5000). Thanks to Frank Gevaerts for testing.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24590 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
3d7983e5c7
commit
0a291fff12
1 changed files with 266 additions and 175 deletions
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@ -24,180 +24,288 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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*/
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/* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned, otherwise it will result either in a data abort, or
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* incorrect results (if ARM aligncheck is disabled). */
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static inline void vector_add(int16_t* v1, int16_t* v2)
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#define FUSED_VECTOR_MATH
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/* Calculate scalarproduct, then add a 2nd vector (fused for performance)
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* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned. It also requires that f2 and s2 are either both 32 bit
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* aligned or both unaligned. If either condition isn't met, it will either
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* result in a data abort or incorrect results. */
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static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
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{
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int res;
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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#define ADDHALFREGS(sum, s1) /* Adds register */ \
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"mov " #s1 ", " #s1 ", ror #16 \n" /* halves straight. */ \
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"add r8 , " #s1 ", " #sum ", lsl #16 \n" /* Clobbers 's1' */ \
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"add " #sum ", " #s1 ", " #sum ", lsr #16 \n" /* and r8. */ \
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"mov " #sum ", " #sum ", lsl #16 \n" \
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"orr " #sum ", " #sum ", r8 , lsr #16 \n"
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#define ADDHALFREGS(sum, s1, s2) /* Adds register */ \
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"mov " #s1 ", " #s1 ", ror #16 \n" /* halves straight */ \
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"add " #sum ", " #s1 ", " #s2 ", lsl #16 \n" /* Clobbers 's1' */ \
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"add " #s1 ", " #s1 ", " #s2 ", lsr #16 \n" \
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"mov " #s1 ", " #s1 ", lsl #16 \n" \
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"orr " #sum ", " #s1 ", " #sum ", lsr #16 \n"
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#define ADDHALFXREGS(sum, s1, s2) /* Adds register */ \
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#define ADDHALFXREGS(sum, s1, s2) /* Adds register */ \
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"add " #s1 ", " #s1 ", " #sum ", lsl #16 \n" /* halves across. */ \
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"add " #sum ", " #s2 ", " #sum ", lsr #16 \n" /* Clobbers 's1'. */ \
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"mov " #sum ", " #sum ", lsl #16 \n" \
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"orr " #sum ", " #sum ", " #s1 ", lsr #16 \n"
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asm volatile (
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"tst %[v2], #2 \n"
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"beq 20f \n"
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"10: \n"
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"ldrh r4, [%[v2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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ADDHALFXREGS(r0, r4, r5)
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ADDHALFXREGS(r1, r5, r6)
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ADDHALFXREGS(r2, r6, r7)
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ADDHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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"mov r4, r8 \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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ADDHALFXREGS(r0, r4, r5)
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ADDHALFXREGS(r1, r5, r6)
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ADDHALFXREGS(r2, r6, r7)
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ADDHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"mov r4, r8 \n"
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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"mov %[res], #0 \n"
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#endif
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"b 99f \n"
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"tst %[f2], #2 \n"
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"beq 20f \n"
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"20: \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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ADDHALFREGS(r0, r4)
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ADDHALFREGS(r1, r5)
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ADDHALFREGS(r2, r6)
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ADDHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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ADDHALFREGS(r0, r4)
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ADDHALFREGS(r1, r5)
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ADDHALFREGS(r2, r6)
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ADDHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"10: \n"
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"ldrh r4, [%[s2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"ldrh r3, [%[f2]], #2 \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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"mov r3, r3, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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#else
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"ldmia %[v1], {r0,r1} \n"
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"smulbb %[res], r0, r3 \n"
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#endif
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r5} \n"
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ADDHALFXREGS(r0, r4, r2)
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ADDHALFXREGS(r1, r2, r5)
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"stmia %[v1]!, {r0,r1} \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r4} \n"
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ADDHALFXREGS(r0, r5, r2)
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ADDHALFXREGS(r1, r2, r4)
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"stmia %[v1]!, {r0,r1} \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r5} \n"
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ADDHALFXREGS(r0, r4, r2)
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ADDHALFXREGS(r1, r2, r5)
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"stmia %[v1]!, {r0,r1} \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r4} \n"
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ADDHALFXREGS(r0, r5, r2)
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ADDHALFXREGS(r1, r2, r4)
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"stmia %[v1]!, {r0,r1} \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"b 99f \n"
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"20: \n"
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"1: \n"
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"ldmia %[v1], {r1,r2} \n"
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"ldmia %[f2]!, {r3,r4} \n"
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#if ORDER > 16
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"smlabb %[res], r1, r3, %[res] \n"
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#else
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"smulbb %[res], r1, r3 \n"
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#endif
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"smlatt %[res], r1, r3, %[res] \n"
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"smlabb %[res], r2, r4, %[res] \n"
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"smlatt %[res], r2, r4, %[res] \n"
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"ldmia %[s2]!, {r3,r4} \n"
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ADDHALFREGS(r0, r1, r3)
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ADDHALFREGS(r1, r2, r4)
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"stmia %[v1]!, {r0,r1} \n"
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".rept 3 \n"
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"ldmia %[v1], {r1,r2} \n"
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"ldmia %[f2]!, {r3,r4} \n"
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"smlabb %[res], r1, r3, %[res] \n"
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"smlatt %[res], r1, r3, %[res] \n"
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"smlabb %[res], r2, r4, %[res] \n"
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"smlatt %[res], r2, r4, %[res] \n"
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"ldmia %[s2]!, {r3,r4} \n"
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ADDHALFREGS(r0, r1, r3)
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ADDHALFREGS(r1, r2, r4)
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"stmia %[v1]!, {r0,r1} \n"
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".endr \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"99: \n"
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"99: \n"
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: /* outputs */
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#if ORDER > 16
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[v2] "+r"(v2)
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[f2] "+r"(f2),
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[s2] "+r"(s2),
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[res]"=r"(res)
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: /* inputs */
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: /* clobbers */
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"r0", "r1", "r2", "r3", "r4",
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"r5", "r6", "r7", "r8", "memory"
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"r0", "r1", "r2", "r3", "r4", "r5", "memory"
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);
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return res;
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}
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/* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned, otherwise it will result either in a data abort, or
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* incorrect results (if ARM aligncheck is disabled). */
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static inline void vector_sub(int16_t* v1, int16_t* v2)
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/* Calculate scalarproduct, then subtract a 2nd vector (fused for performance)
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* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned. It also requires that f2 and s2 are either both 32 bit
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* aligned or both unaligned. If either condition isn't met, it will either
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* result in a data abort or incorrect results. */
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static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
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{
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int res;
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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#define SUBHALFREGS(dif, s1) /* Subtracts register */ \
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"sub r8 , " #dif ", " #s1 "\n" /* halves straight. */ \
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"and r8 , r8 , r9 \n" /* Needs r9 = 0x0000ffff, */ \
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"mov " #dif ", " #dif ", lsr #16 \n" /* clobbers r8. */ \
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"sub " #dif ", " #dif ", " #s1 ", lsr #16 \n" \
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"orr " #dif ", r8 , " #dif ", lsl #16 \n"
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#define SUBHALFREGS(dif, s1, s2) /* Subtracts reg. */ \
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"mov " #s1 ", " #s1 ", ror #16 \n" /* halves straight */ \
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"sub " #dif ", " #s1 ", " #s2 ", lsl #16 \n" /* Clobbers 's1' */ \
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"sub " #s1 ", " #s1 ", " #s2 ", lsr #16 \n" \
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"mov " #s1 ", " #s1 ", lsl #16 \n" \
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"orr " #dif ", " #s1 ", " #dif ", lsr #16 \n"
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#define SUBHALFXREGS(dif, s1, s2, msk) /* Subtracts reg. */ \
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"sub " #s1 ", " #dif ", " #s1 ", lsr #16 \n" /* halves across. */ \
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"and " #s1 ", " #s1 ", " #msk " \n" /* Needs msk = */ \
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"rsb " #dif ", " #s2 ", " #dif ", lsr #16 \n" /* 0x0000ffff, */ \
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"orr " #dif ", " #s1 ", " #dif ", lsl #16 \n" /* clobbers 's1'. */
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#define SUBHALFXREGS(dif, s1, s2) /* Subtracts register */ \
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"sub " #s1 ", " #dif ", " #s1 ", lsr #16 \n" /* halves across. */ \
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"and " #s1 ", " #s1 ", r9 \n" /* Needs r9 = 0x0000ffff, */ \
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"rsb " #dif ", " #s2 ", " #dif ", lsr #16 \n" /* clobbers 's1'. */ \
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"orr " #dif ", " #s1 ", " #dif ", lsl #16 \n"
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asm volatile (
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"mov r9, #0xff \n"
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"orr r9, r9, #0xff00 \n"
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"tst %[v2], #2 \n"
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"beq 20f \n"
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"10: \n"
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"ldrh r4, [%[v2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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SUBHALFXREGS(r0, r4, r5)
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SUBHALFXREGS(r1, r5, r6)
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SUBHALFXREGS(r2, r6, r7)
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SUBHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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"mov r4, r8 \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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SUBHALFXREGS(r0, r4, r5)
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SUBHALFXREGS(r1, r5, r6)
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SUBHALFXREGS(r2, r6, r7)
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SUBHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"mov r4, r8 \n"
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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"mov %[res], #0 \n"
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#endif
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"b 99f \n"
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"tst %[f2], #2 \n"
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"beq 20f \n"
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"20: \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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SUBHALFREGS(r0, r4)
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SUBHALFREGS(r1, r5)
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SUBHALFREGS(r2, r6)
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SUBHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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SUBHALFREGS(r0, r4)
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SUBHALFREGS(r1, r5)
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SUBHALFREGS(r2, r6)
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SUBHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"10: \n"
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"mov r6, #0xff \n"
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"orr r6, r6, #0xff00 \n"
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"ldrh r4, [%[s2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"ldrh r3, [%[f2]], #2 \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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"mov r3, r3, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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#else
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"ldmia %[v1], {r0,r1} \n"
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"smulbb %[res], r0, r3 \n"
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#endif
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r5} \n"
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SUBHALFXREGS(r0, r4, r2, r6)
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SUBHALFXREGS(r1, r2, r5, r6)
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"stmia %[v1]!, {r0,r1} \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
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"smlatb %[res], r1, r3, %[res] \n"
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"ldmia %[s2]!, {r2,r4} \n"
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SUBHALFXREGS(r0, r5, r2, r6)
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SUBHALFXREGS(r1, r2, r4, r6)
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"stmia %[v1]!, {r0,r1} \n"
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"ldmia %[v1], {r0,r1} \n"
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"smlabt %[res], r0, r3, %[res] \n"
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"ldmia %[f2]!, {r2,r3} \n"
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"smlatb %[res], r0, r2, %[res] \n"
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"smlabt %[res], r1, r2, %[res] \n"
|
||||
"smlatb %[res], r1, r3, %[res] \n"
|
||||
"ldmia %[s2]!, {r2,r5} \n"
|
||||
SUBHALFXREGS(r0, r4, r2, r6)
|
||||
SUBHALFXREGS(r1, r2, r5, r6)
|
||||
"stmia %[v1]!, {r0,r1} \n"
|
||||
"ldmia %[v1], {r0,r1} \n"
|
||||
"smlabt %[res], r0, r3, %[res] \n"
|
||||
"ldmia %[f2]!, {r2,r3} \n"
|
||||
"smlatb %[res], r0, r2, %[res] \n"
|
||||
"smlabt %[res], r1, r2, %[res] \n"
|
||||
"smlatb %[res], r1, r3, %[res] \n"
|
||||
"ldmia %[s2]!, {r2,r4} \n"
|
||||
SUBHALFXREGS(r0, r5, r2, r6)
|
||||
SUBHALFXREGS(r1, r2, r4, r6)
|
||||
"stmia %[v1]!, {r0,r1} \n"
|
||||
#if ORDER > 16
|
||||
"subs %[cnt], %[cnt], #1 \n"
|
||||
"bne 1b \n"
|
||||
#endif
|
||||
"b 99f \n"
|
||||
|
||||
"20: \n"
|
||||
"1: \n"
|
||||
"ldmia %[v1], {r1,r2} \n"
|
||||
"ldmia %[f2]!, {r3,r4} \n"
|
||||
#if ORDER > 16
|
||||
"smlabb %[res], r1, r3, %[res] \n"
|
||||
#else
|
||||
"smulbb %[res], r1, r3 \n"
|
||||
#endif
|
||||
"smlatt %[res], r1, r3, %[res] \n"
|
||||
"smlabb %[res], r2, r4, %[res] \n"
|
||||
"smlatt %[res], r2, r4, %[res] \n"
|
||||
"ldmia %[s2]!, {r3,r4} \n"
|
||||
SUBHALFREGS(r0, r1, r3)
|
||||
SUBHALFREGS(r1, r2, r4)
|
||||
"stmia %[v1]!, {r0,r1} \n"
|
||||
|
||||
".rept 3 \n"
|
||||
"ldmia %[v1], {r1,r2} \n"
|
||||
"ldmia %[f2]!, {r3,r4} \n"
|
||||
"smlabb %[res], r1, r3, %[res] \n"
|
||||
"smlatt %[res], r1, r3, %[res] \n"
|
||||
"smlabb %[res], r2, r4, %[res] \n"
|
||||
"smlatt %[res], r2, r4, %[res] \n"
|
||||
"ldmia %[s2]!, {r3,r4} \n"
|
||||
SUBHALFREGS(r0, r1, r3)
|
||||
SUBHALFREGS(r1, r2, r4)
|
||||
"stmia %[v1]!, {r0,r1} \n"
|
||||
".endr \n"
|
||||
#if ORDER > 16
|
||||
"subs %[cnt], %[cnt], #1 \n"
|
||||
"bne 1b \n"
|
||||
#endif
|
||||
|
||||
"99: \n"
|
||||
"99: \n"
|
||||
: /* outputs */
|
||||
#if ORDER > 16
|
||||
[cnt]"+r"(cnt),
|
||||
#endif
|
||||
[v1] "+r"(v1),
|
||||
[v2] "+r"(v2)
|
||||
[f2] "+r"(f2),
|
||||
[s2] "+r"(s2),
|
||||
[res]"=r"(res)
|
||||
: /* inputs */
|
||||
: /* clobbers */
|
||||
"r0", "r1", "r2", "r3", "r4", "r5",
|
||||
"r6", "r7", "r8", "r9", "memory"
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory"
|
||||
);
|
||||
return res;
|
||||
}
|
||||
|
||||
/* This version fetches data as 32 bit words, and *requires* v1 to be
|
||||
|
|
@ -211,9 +319,9 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
|
|||
#endif
|
||||
|
||||
#if ORDER > 16
|
||||
#define MLA_BLOCKS "3"
|
||||
#define MLA_BLOCKS "7"
|
||||
#else
|
||||
#define MLA_BLOCKS "1"
|
||||
#define MLA_BLOCKS "3"
|
||||
#endif
|
||||
|
||||
asm volatile (
|
||||
|
|
@ -224,36 +332,28 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
|
|||
"beq 20f \n"
|
||||
|
||||
"10: \n"
|
||||
"ldrh r7, [%[v2]], #2 \n"
|
||||
"ldrh r3, [%[v2]], #2 \n"
|
||||
#if ORDER > 32
|
||||
"mov r7, r7, lsl #16 \n"
|
||||
"mov r3, r3, lsl #16 \n"
|
||||
"1: \n"
|
||||
"ldmia %[v1]!, {r0-r3} \n"
|
||||
"smlabt %[res], r0, r7, %[res] \n"
|
||||
"ldmia %[v1]!, {r0,r1} \n"
|
||||
"smlabt %[res], r0, r3, %[res] \n"
|
||||
#else
|
||||
"ldmia %[v1]!, {r0-r3} \n"
|
||||
"smulbb %[res], r0, r7 \n"
|
||||
"ldmia %[v1]!, {r0,r1} \n"
|
||||
"smulbb %[res], r0, r3 \n"
|
||||
#endif
|
||||
"ldmia %[v2]!, {r4-r7} \n"
|
||||
"smlatb %[res], r0, r4, %[res] \n"
|
||||
"smlabt %[res], r1, r4, %[res] \n"
|
||||
"smlatb %[res], r1, r5, %[res] \n"
|
||||
"smlabt %[res], r2, r5, %[res] \n"
|
||||
"smlatb %[res], r2, r6, %[res] \n"
|
||||
"smlabt %[res], r3, r6, %[res] \n"
|
||||
"smlatb %[res], r3, r7, %[res] \n"
|
||||
|
||||
"ldmia %[v2]!, {r2,r3} \n"
|
||||
"smlatb %[res], r0, r2, %[res] \n"
|
||||
"smlabt %[res], r1, r2, %[res] \n"
|
||||
"smlatb %[res], r1, r3, %[res] \n"
|
||||
|
||||
".rept " MLA_BLOCKS "\n"
|
||||
"ldmia %[v1]!, {r0-r3} \n"
|
||||
"smlabt %[res], r0, r7, %[res] \n"
|
||||
"ldmia %[v2]!, {r4-r7} \n"
|
||||
"smlatb %[res], r0, r4, %[res] \n"
|
||||
"smlabt %[res], r1, r4, %[res] \n"
|
||||
"smlatb %[res], r1, r5, %[res] \n"
|
||||
"smlabt %[res], r2, r5, %[res] \n"
|
||||
"smlatb %[res], r2, r6, %[res] \n"
|
||||
"smlabt %[res], r3, r6, %[res] \n"
|
||||
"smlatb %[res], r3, r7, %[res] \n"
|
||||
"ldmia %[v1]!, {r0,r1} \n"
|
||||
"smlabt %[res], r0, r3, %[res] \n"
|
||||
"ldmia %[v2]!, {r2,r3} \n"
|
||||
"smlatb %[res], r0, r2, %[res] \n"
|
||||
"smlabt %[res], r1, r2, %[res] \n"
|
||||
"smlatb %[res], r1, r3, %[res] \n"
|
||||
".endr \n"
|
||||
#if ORDER > 32
|
||||
"subs %[cnt], %[cnt], #1 \n"
|
||||
|
|
@ -263,32 +363,24 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
|
|||
|
||||
"20: \n"
|
||||
"1: \n"
|
||||
"ldmia %[v1]!, {r0-r3} \n"
|
||||
"ldmia %[v2]!, {r4-r7} \n"
|
||||
"ldmia %[v1]!, {r0,r1} \n"
|
||||
"ldmia %[v2]!, {r2,r3} \n"
|
||||
#if ORDER > 32
|
||||
"smlabb %[res], r0, r4, %[res] \n"
|
||||
"smlabb %[res], r0, r2, %[res] \n"
|
||||
#else
|
||||
"smulbb %[res], r0, r4 \n"
|
||||
"smulbb %[res], r0, r2 \n"
|
||||
#endif
|
||||
"smlatt %[res], r0, r4, %[res] \n"
|
||||
"smlabb %[res], r1, r5, %[res] \n"
|
||||
"smlatt %[res], r1, r5, %[res] \n"
|
||||
"smlabb %[res], r2, r6, %[res] \n"
|
||||
"smlatt %[res], r2, r6, %[res] \n"
|
||||
"smlabb %[res], r3, r7, %[res] \n"
|
||||
"smlatt %[res], r3, r7, %[res] \n"
|
||||
"smlatt %[res], r0, r2, %[res] \n"
|
||||
"smlabb %[res], r1, r3, %[res] \n"
|
||||
"smlatt %[res], r1, r3, %[res] \n"
|
||||
|
||||
".rept " MLA_BLOCKS "\n"
|
||||
"ldmia %[v1]!, {r0-r3} \n"
|
||||
"ldmia %[v2]!, {r4-r7} \n"
|
||||
"smlabb %[res], r0, r4, %[res] \n"
|
||||
"smlatt %[res], r0, r4, %[res] \n"
|
||||
"smlabb %[res], r1, r5, %[res] \n"
|
||||
"smlatt %[res], r1, r5, %[res] \n"
|
||||
"smlabb %[res], r2, r6, %[res] \n"
|
||||
"smlatt %[res], r2, r6, %[res] \n"
|
||||
"smlabb %[res], r3, r7, %[res] \n"
|
||||
"smlatt %[res], r3, r7, %[res] \n"
|
||||
"ldmia %[v1]!, {r0,r1} \n"
|
||||
"ldmia %[v2]!, {r2,r3} \n"
|
||||
"smlabb %[res], r0, r2, %[res] \n"
|
||||
"smlatt %[res], r0, r2, %[res] \n"
|
||||
"smlabb %[res], r1, r3, %[res] \n"
|
||||
"smlatt %[res], r1, r3, %[res] \n"
|
||||
".endr \n"
|
||||
#if ORDER > 32
|
||||
"subs %[cnt], %[cnt], #1 \n"
|
||||
|
|
@ -305,8 +397,7 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
|
|||
[res]"=r"(res)
|
||||
: /* inputs */
|
||||
: /* clobbers */
|
||||
"r0", "r1", "r2", "r3",
|
||||
"r4", "r5", "r6", "r7"
|
||||
"r0", "r1", "r2", "r3"
|
||||
);
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue