Add preliminary support for the Onda VX747 (MIPS target)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18032 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
4f19981748
commit
0709f0a5c6
27 changed files with 10853 additions and 0 deletions
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@ -31,4 +31,6 @@ mrobe500.c
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telechips.c
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#elif defined(MEIZU_M6SL)
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meizu_m6sl.c
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#elif defined(ONDA_VX747)
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ondavx747.c
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#endif
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125
bootloader/ondavx747.c
Executable file
125
bootloader/ondavx747.c
Executable file
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@ -0,0 +1,125 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include "config.h"
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#include "jz4740.h"
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#include "backlight.h"
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#include "font.h"
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#include "lcd.h"
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#include "system.h"
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#include "mips.h"
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#include "button.h"
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int _line = 1;
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char _printfbuf[256];
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/* This is all rather hacky, but it works... */
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void _printf(const char *format, ...)
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{
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int len;
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unsigned char *ptr;
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va_list ap;
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va_start(ap, format);
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ptr = _printfbuf;
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len = vsnprintf(ptr, sizeof(_printfbuf), format, ap);
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va_end(ap);
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int i;
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for(i=0; i<1; i++)
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{
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lcd_puts(0, _line++, ptr);
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lcd_update();
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}
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if(_line >= LCD_HEIGHT/SYSFONT_HEIGHT)
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_line = 1;
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}
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void audiotest(void)
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{
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__i2s_internal_codec();
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__aic_enable();
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__aic_reset();
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__aic_select_i2s();
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__aic_enable_loopback();
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}
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static void jz_store_icache(void)
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{
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unsigned long start;
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unsigned long end;
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start = KSEG0BASE;
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end = start + CFG_ICACHE_SIZE;
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while(start < end)
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{
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cache_unroll(start, 8);
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start += CFG_CACHELINE_SIZE;
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}
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}
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int main(void)
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{
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cli();
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write_c0_status(0x10000400);
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memcpy((void *)A_K0BASE, (void *)0x80E00080, 0x20);
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memcpy((void *)(A_K0BASE + 0x180), (void *)0x80E00080, 0x20);
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memcpy((void *)(A_K0BASE + 0x200), (void *)0x80E00080, 0x20);
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jz_flush_dcache();
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jz_store_icache();
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sti();
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kernel_init();
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lcd_init();
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font_init();
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lcd_setfont(FONT_SYSFIXED);
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button_init();
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backlight_init();
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/* To make the Windows say "ding-dong".. */
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REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
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int touch;
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lcd_clear_display();
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_printf("Rockbox bootloader v0.000001");
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while(1)
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{
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if(button_read_device(&touch) & BUTTON_VOL_DOWN)
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_printf("BUTTON_VOL_DOWN");
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if(button_read_device(&touch) & BUTTON_MENU)
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_printf("BUTTON_MENU");
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if(button_read_device(&touch) & BUTTON_VOL_UP)
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_printf("BUTTON_VOL_UP");
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if(button_read_device(&touch) & BUTTON_POWER)
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_printf("BUTTON_POWER");
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_printf("X: %d Y: %d", touch>>16, touch&0xFFFF);
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}
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return 0;
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}
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@ -325,9 +325,11 @@ target/arm/i2c-telechips.c
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#elif CONFIG_I2C == I2C_S3C2440
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/* no i2c driver yet */
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#endif
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#if CONFIG_CPU == PNX0101
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target/arm/pnx0101/system-pnx0101.c
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#endif
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#if defined(CPU_PP)
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#if CONFIG_CPU == PP5002
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target/arm/system-pp5002.c
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@ -362,6 +364,21 @@ target/arm/crt0.S
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#endif /* defined(CPU_*) */
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#endif /* SIMULATOR */
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#elif defined(CPU_MIPS)
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#undef mips
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/*target/mips/memcpy.S
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target/mips/memset.S
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common/memset16.c
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target/mips/strlen.S*/
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common/memcpy.c
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common/memmove.c
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common/memset.c
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common/memset16.c
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common/strlen.c
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#if CONFIG_CPU==JZ4732
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target/mips/ingenic_jz47xx/crt0.S
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#endif /* CONFIG_CPU == JZ4732 */
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#else
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#ifdef HAVE_PRIORITY_SCHEDULING
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@ -1054,3 +1071,15 @@ target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
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#endif /* BOOTLOADER */
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#endif /* SIMULATOR */
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#endif /* MEIZU_M6SL */
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#if CONFIG_CPU==JZ4732
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target/mips/ingenic_jz47xx/ata-jz4740.c
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target/mips/ingenic_jz47xx/lcd-jz4740.c
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target/mips/ingenic_jz47xx/system-jz4740.c
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#endif
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#ifdef ONDA_VX747
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target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
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target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
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target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
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#endif
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170
firmware/export/config-ondavx747.h
Executable file
170
firmware/export/config-ondavx747.h
Executable file
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@ -0,0 +1,170 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* This config file is for the Onda VX747
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*/
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#define TARGET_TREE /* this target is using the target tree system */
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#define CONFIG_SDRAM_START 0x80E00000 /* HACK! */
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#define ONDA_VX747 1
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/* For Rolo and boot loader */
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#define MODEL_NUMBER 30
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/* define this if you use an ATA controller */
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//#define HAVE_ATA
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/* define this if you have a bitmap LCD display */
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#define HAVE_LCD_BITMAP
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/* define this if you have a colour LCD */
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#define HAVE_LCD_COLOR
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/* define this if you have access to the quickscreen */
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#define HAVE_QUICKSCREEN
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/* define this if you have access to the pitchscreen */
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#define HAVE_PITCHSCREEN
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/* define this if you would like tagcache to build on this target */
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#define HAVE_TAGCACHE
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/* define this if the target has volume keys which can be used in the lists */
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#define HAVE_VOLUME_IN_LIST
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/* LCD dimensions */
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#define CONFIG_LCD LCD_ONDAVX747
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/* choose the lcd orientation. both work */
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#define CONFIG_ORIENTATION SCREEN_PORTRAIT
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#define LCD_WIDTH 400
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#define LCD_HEIGHT 240
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#define LCD_DEPTH 16 /* 16bit colours */
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#define LCD_PIXELFORMAT RGB565 /* rgb565 */
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/* Define this if your LCD can be enabled/disabled */
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#define HAVE_LCD_ENABLE
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#define CONFIG_KEYPAD ONDAVX747_PAD
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#define HAS_BUTTON_HOLD
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//#define HAVE_HEADPHONE_DETECTION
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#define HAVE_TOUCHPAD
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#define HAVE_BUTTON_DATA
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/* Define this if you do software codec */
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#define CONFIG_CODEC SWCODEC
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/* define this if you have a real-time clock */
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//#define CONFIG_RTC RTC_RX5X348AB
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/* Define this for LCD backlight available */
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#define HAVE_BACKLIGHT
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#define HAVE_BACKLIGHT_BRIGHTNESS
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/* Main LCD backlight brightness range and defaults */
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#define MIN_BRIGHTNESS_SETTING 0 /* TODO */
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#define MAX_BRIGHTNESS_SETTING 127
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#define DEFAULT_BRIGHTNESS_SETTING 85
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#define DEFAULT_DIMNESS_SETTING 22
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/* Define this if you have a software controlled poweroff */
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//#define HAVE_SW_POWEROFF
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//TODO: enable this back
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/* The number of bytes reserved for loadable codecs */
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#define CODEC_SIZE 0x80000
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/* The number of bytes reserved for loadable plugins */
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#define PLUGIN_BUFFER_SIZE 0x100000
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/* Define this if you have the */
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//#define HAVE_TLV320
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#define CONFIG_I2C I2C_JZ47XX
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/* TLV320 has no tone controls, so we use the software ones */
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//#define HAVE_SW_TONE_CONTROLS
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/*#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
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SAMPR_CAP_11)*/
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#define BATTERY_CAPACITY_DEFAULT 1250 /* default battery capacity */
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#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
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#define BATTERY_CAPACITY_MAX 2500 /* max. capacity selectable */
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#define BATTERY_CAPACITY_INC 100 /* capacity increment */
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#define BATTERY_TYPES_COUNT 1 /* only one type */
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/* Hardware controlled charging with monitoring */
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//#define CONFIG_CHARGING CHARGING_MONITOR
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#ifndef SIMULATOR
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/* Define this if you have a Ingenic JZ4732 */
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#define CONFIG_CPU JZ4732
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/* define this if the hardware can be powered off while charging */
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#define HAVE_POWEROFF_WHILE_CHARGING
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/* Define this to the CPU frequency */
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#define CPU_FREQ 16934400
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/* define this if you have a flash memory storage */
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#define HAVE_FLASH_STORAGE
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/* Virtual LED (icon) */
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#define CONFIG_LED LED_VIRTUAL
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/* define this if the backlight can be set to a brightness */
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#define __BACKLIGHT_INIT
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/* Offset ( in the firmware file's header ) to the file CRC */
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#define FIRMWARE_OFFSET_FILE_CRC 0
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/* Offset ( in the firmware file's header ) to the real data */
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#define FIRMWARE_OFFSET_FILE_DATA 8
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/* Define this if you have adjustable CPU frequency */
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/* #define HAVE_ADJUSTABLE_CPU_FREQ */
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#define BOOTFILE_EXT "vx747"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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/*#define CONFIG_USBOTG USBOTG_INGENIC
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#define HAVE_USBSTACK
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#define USB_VENDOR_ID 0x041e
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#define USB_PRODUCT_ID 0x4133*/
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/*DEBUGGING!*/
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#ifdef BOOTLOADER
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#define THREAD_EXTRA_CHECKS 1
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#define DEBUG 1
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#define debug(msg) printf(msg)
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#endif
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#include <stdbool.h> /* HACKY */
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#endif
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@ -60,6 +60,7 @@
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#define TCC773L 773
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#define TCC7801 7801
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#define S5L8700 8700
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#define JZ4732 4732
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/* CONFIG_KEYPAD */
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#define PLAYER_PAD 1
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@ -92,6 +93,7 @@
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#define SANSA_C100_PAD 28
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#define PHILIPS_HDD1630_PAD 29
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#define MEIZU_M6SL_PAD 30
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#define ONDAVX747_PAD 31
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/* CONFIG_REMOTE_KEYPAD */
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#define H100_REMOTE 1
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@ -134,6 +136,7 @@
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#define LCD_S6B33B2 26 /* as used by the Sansa c100 */
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#define LCD_HDD1630 27 /* as used by the Philips HDD1630 */
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#define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */
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#define LCD_ONDAVX747 29 /* as used by the Onda VX747 */
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/* LCD_PIXELFORMAT */
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#define HORIZONTAL_PACKING 1
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@ -162,6 +165,7 @@
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#define I2C_TCC780X 11
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#define I2C_DM320 12 /* DM320 style */
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#define I2C_S5L8700 13
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#define I2C_JZ47XX 14 /* Ingenic Jz47XX style */
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/* CONFIG_LED */
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#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
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@ -187,12 +191,14 @@
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#define RTC_MC13783 13 /* Freescale MC13783 PMIC */
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#define RTC_S5L8700 14
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#define RTC_S35390A 15
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#define RTC_JZ47XX 16 /* Ingenic Jz47XX */
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/* USB On-the-go */
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#define USBOTG_ISP1362 1362 /* iriver H300 */
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#define USBOTG_ISP1583 1583 /* Creative Zen Vision:M */
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#define USBOTG_M5636 5636 /* iAudio X5 */
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#define USBOTG_ARC 5020 /* PortalPlayer 502x */
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#define USBOTG_JZ4740 4740 /* Ingenic Jz4740/Jz4732 */
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/* Multiple cores */
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#define CPU 0
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@ -283,6 +289,8 @@
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#include "config-c100.h"
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#elif defined(MEIZU_M6SL)
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#include "config-meizu-m6sl.h"
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#elif defined(ONDA_VX747)
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#include "config-ondavx747.h"
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#else
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/* no known platform */
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#endif
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@ -448,6 +456,10 @@
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#define ROCKBOX_STRICT_ALIGN 1
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#endif
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#if (CONFIG_CPU == JZ4732)
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#define CPU_MIPS 32
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#endif
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#ifndef CODEC_SIZE
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#define CODEC_SIZE 0
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#endif
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4902
firmware/export/jz4740.h
Executable file
4902
firmware/export/jz4740.h
Executable file
File diff suppressed because it is too large
Load diff
2356
firmware/export/mips-archdefs.h
Executable file
2356
firmware/export/mips-archdefs.h
Executable file
File diff suppressed because it is too large
Load diff
820
firmware/export/mips.h
Executable file
820
firmware/export/mips.h
Executable file
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@ -0,0 +1,820 @@
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/**************************************************************************
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* *
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* PROJECT : MIPS port for uC/OS-II *
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* *
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* MODULE : MIPS.h *
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* *
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* AUTHOR : Michael Anburaj *
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* URL : http://geocities.com/michaelanburaj/ *
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* EMAIL: michaelanburaj@hotmail.com *
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* *
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* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
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* *
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* TOOL-CHAIN : SDE & Cygnus *
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* *
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* DESCRIPTION : *
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* MIPS processor definitions. *
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* The basic CPU definitions are found in the file archdefs.h, which *
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* is included by mips.h. *
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* *
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* mips.h implements aliases for some of the definitions in archdefs.h *
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* and adds various definitions. *
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* *
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**************************************************************************/
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#ifndef __MIPS_H__
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#define __MIPS_H__
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#include "mips-archdefs.h"
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/* ********************************************************************* */
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/* Module configuration */
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/* ********************************************************************* */
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/* Interface macro & data definition */
|
||||
|
||||
#ifndef MSK
|
||||
#define MSK(n) ((1 << (n)) - 1)
|
||||
#endif
|
||||
|
||||
/* CPU registers */
|
||||
#define SYS_CPUREG_ZERO 0
|
||||
#define SYS_CPUREG_AT 1
|
||||
#define SYS_CPUREG_V0 2
|
||||
#define SYS_CPUREG_V1 3
|
||||
#define SYS_CPUREG_A0 4
|
||||
#define SYS_CPUREG_A1 5
|
||||
#define SYS_CPUREG_A2 6
|
||||
#define SYS_CPUREG_A3 7
|
||||
#define SYS_CPUREG_T0 8
|
||||
#define SYS_CPUREG_T1 9
|
||||
#define SYS_CPUREG_T2 10
|
||||
#define SYS_CPUREG_T3 11
|
||||
#define SYS_CPUREG_T4 12
|
||||
#define SYS_CPUREG_T5 13
|
||||
#define SYS_CPUREG_T6 14
|
||||
#define SYS_CPUREG_T7 15
|
||||
#define SYS_CPUREG_S0 16
|
||||
#define SYS_CPUREG_S1 17
|
||||
#define SYS_CPUREG_S2 18
|
||||
#define SYS_CPUREG_S3 19
|
||||
#define SYS_CPUREG_S4 20
|
||||
#define SYS_CPUREG_S5 21
|
||||
#define SYS_CPUREG_S6 22
|
||||
#define SYS_CPUREG_S7 23
|
||||
#define SYS_CPUREG_T8 24
|
||||
#define SYS_CPUREG_T9 25
|
||||
#define SYS_CPUREG_K0 26
|
||||
#define SYS_CPUREG_K1 27
|
||||
#define SYS_CPUREG_GP 28
|
||||
#define SYS_CPUREG_SP 29
|
||||
#define SYS_CPUREG_S8 30
|
||||
#define SYS_CPUREG_FP SYS_CPUREG_S8
|
||||
#define SYS_CPUREG_RA 31
|
||||
|
||||
|
||||
/* CPU register fp ($30) has an alias s8 */
|
||||
#define s8 fp
|
||||
|
||||
|
||||
/* Aliases for System Control Coprocessor (CP0) registers */
|
||||
#define C0_INDEX C0_Index
|
||||
#define C0_RANDOM C0_Random
|
||||
#define C0_ENTRYLO0 C0_EntryLo0
|
||||
#define C0_ENTRYLO1 C0_EntryLo1
|
||||
#define C0_CONTEXT C0_Context
|
||||
#define C0_PAGEMASK C0_PageMask
|
||||
#define C0_WIRED C0_Wired
|
||||
#define C0_BADVADDR C0_BadVAddr
|
||||
#define C0_COUNT C0_Count
|
||||
#define C0_ENTRYHI C0_EntryHi
|
||||
#define C0_COMPARE C0_Compare
|
||||
#define C0_STATUS C0_Status
|
||||
#define C0_CAUSE C0_Cause
|
||||
|
||||
#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
|
||||
#undef C0_PRID
|
||||
#endif
|
||||
#define C0_PRID C0_PRId
|
||||
|
||||
#define C0_CONFIG C0_Config
|
||||
#define C0_CONFIG1 C0_Config1
|
||||
#define C0_LLADDR C0_LLAddr
|
||||
#define C0_WATCHLO C0_WatchLo
|
||||
#define C0_WATCHHI C0_WatchHi
|
||||
#define C0_DEBUG C0_Debug
|
||||
#define C0_PERFCNT C0_PerfCnt
|
||||
#define C0_ERRCTL C0_ErrCtl
|
||||
#define C0_CACHEERR C0_CacheErr
|
||||
#define C0_TAGLO C0_TagLo
|
||||
#define C0_DATALO C0_DataLo
|
||||
#define C0_TAGHI C0_TagHi
|
||||
#define C0_DATAHI C0_DataHi
|
||||
#define C0_ERROREPC C0_ErrorEPC
|
||||
#if 0
|
||||
#define C0_DESAVE C0_DESAVE
|
||||
#define C0_EPC C0_EPC
|
||||
#define C0_DEPC C0_DEPC
|
||||
#endif
|
||||
|
||||
/* System Control Coprocessor (CP0) registers select fields */
|
||||
#define C0_INDEX_SEL 0 /* TLB Index */
|
||||
#define C0_RANDOM_SEL 0 /* TLB Random */
|
||||
#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
|
||||
#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
|
||||
#define C0_CONTEXT_SEL 0 /* Context */
|
||||
#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
|
||||
#define C0_WIRED_SEL 0 /* TLB Wired */
|
||||
#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
|
||||
#define C0_COUNT_SEL 0 /* Count */
|
||||
#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
|
||||
#define C0_COMPARE_SEL 0 /* Compare */
|
||||
#define C0_STATUS_SEL 0 /* Processor Status */
|
||||
#define C0_CAUSE_SEL 0 /* Exception Cause */
|
||||
#define C0_EPC_SEL 0 /* Exception PC */
|
||||
#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
|
||||
#define C0_CONFIG_SEL 0 /* Config */
|
||||
#define C0_CONFIG1_SEL 1 /* Config1 */
|
||||
#define C0_LLADDR_SEL 0 /* LLAddr */
|
||||
#define C0_WATCHLO_SEL 0 /* WatchpointLo */
|
||||
#define C0_WATCHHI_SEL 0 /* WatchpointHi */
|
||||
#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
|
||||
#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
|
||||
#define C0_PERFCNT_SEL 0 /* Performance counter interface */
|
||||
#define C0_ERRCTL_SEL 0 /* ERRCTL */
|
||||
#define C0_CACHEERR_SEL 0 /* CacheErr */
|
||||
#define C0_TAGLO_SEL 0 /* TagLo */
|
||||
#define C0_DATALO_SEL 1 /* DataLo */
|
||||
#define C0_DTAGLO_SEL 2 /* DTagLo */
|
||||
#define C0_TAGHI_SEL 0 /* TagHi */
|
||||
#define C0_DATAHI_SEL 1 /* DataHi */
|
||||
#define C0_DTAGHI_SEL 2 /* DTagHi */
|
||||
#define C0_ERROREPC_SEL 0 /* ErrorEPC */
|
||||
#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
|
||||
|
||||
|
||||
/* C0_CONFIG register encoding */
|
||||
|
||||
#define C0_CONFIG_M_SHF S_ConfigMore
|
||||
#define C0_CONFIG_M_MSK M_ConfigMore
|
||||
#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
|
||||
|
||||
#define C0_CONFIG_BE_SHF S_ConfigBE
|
||||
#define C0_CONFIG_BE_MSK M_ConfigBE
|
||||
#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
|
||||
|
||||
#define C0_CONFIG_AT_SHF S_ConfigAT
|
||||
#define C0_CONFIG_AT_MSK M_ConfigAT
|
||||
#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
|
||||
#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
|
||||
#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
|
||||
|
||||
#define C0_CONFIG_AR_SHF S_ConfigAR
|
||||
#define C0_CONFIG_AR_MSK M_ConfigAR
|
||||
|
||||
#define C0_CONFIG_MT_SHF S_ConfigMT
|
||||
#define C0_CONFIG_MT_MSK M_ConfigMT
|
||||
#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
|
||||
#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
|
||||
#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
|
||||
#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
|
||||
|
||||
#define C0_CONFIG_K0_SHF S_ConfigK0
|
||||
#define C0_CONFIG_K0_MSK M_ConfigK0
|
||||
#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
|
||||
#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
|
||||
#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
|
||||
#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
|
||||
#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
|
||||
#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
|
||||
#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
|
||||
#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
|
||||
|
||||
|
||||
/* WC field.
|
||||
*
|
||||
* This feature is present specifically to support configuration
|
||||
* testing of the core in a lead vehicle, and is not supported
|
||||
* in any other environment. Attempting to use this feature
|
||||
* outside of the scope of a lead vehicle is a violation of the
|
||||
* MIPS Architecture, and may cause unpredictable operation of
|
||||
* the processor.
|
||||
*/
|
||||
#define C0_CONFIG_WC_SHF 19
|
||||
#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
|
||||
#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
|
||||
|
||||
|
||||
/* C0_CONFIG1 register encoding */
|
||||
|
||||
#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
|
||||
#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
|
||||
|
||||
#define C0_CONFIG1_IS_SHF S_Config1IS
|
||||
#define C0_CONFIG1_IS_MSK M_Config1IS
|
||||
|
||||
#define C0_CONFIG1_IL_SHF S_Config1IL
|
||||
#define C0_CONFIG1_IL_MSK M_Config1IL
|
||||
|
||||
#define C0_CONFIG1_IA_SHF S_Config1IA
|
||||
#define C0_CONFIG1_IA_MSK M_Config1IA
|
||||
|
||||
#define C0_CONFIG1_DS_SHF S_Config1DS
|
||||
#define C0_CONFIG1_DS_MSK M_Config1DS
|
||||
|
||||
#define C0_CONFIG1_DL_SHF S_Config1DL
|
||||
#define C0_CONFIG1_DL_MSK M_Config1DL
|
||||
|
||||
#define C0_CONFIG1_DA_SHF S_Config1DA
|
||||
#define C0_CONFIG1_DA_MSK M_Config1DA
|
||||
|
||||
#define C0_CONFIG1_WR_SHF S_Config1WR
|
||||
#define C0_CONFIG1_WR_MSK M_Config1WR
|
||||
#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
|
||||
|
||||
#define C0_CONFIG1_CA_SHF S_Config1CA
|
||||
#define C0_CONFIG1_CA_MSK M_Config1CA
|
||||
#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
|
||||
|
||||
#define C0_CONFIG1_EP_SHF S_Config1EP
|
||||
#define C0_CONFIG1_EP_MSK M_Config1EP
|
||||
#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
|
||||
|
||||
#define C0_CONFIG1_FP_SHF S_Config1FP
|
||||
#define C0_CONFIG1_FP_MSK M_Config1FP
|
||||
#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
|
||||
|
||||
|
||||
/* C0_STATUS register encoding */
|
||||
|
||||
#define C0_STATUS_CU3_SHF S_StatusCU3
|
||||
#define C0_STATUS_CU3_MSK M_StatusCU3
|
||||
#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
|
||||
|
||||
#define C0_STATUS_CU2_SHF S_StatusCU2
|
||||
#define C0_STATUS_CU2_MSK M_StatusCU2
|
||||
#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
|
||||
|
||||
#define C0_STATUS_CU1_SHF S_StatusCU1
|
||||
#define C0_STATUS_CU1_MSK M_StatusCU1
|
||||
#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
|
||||
|
||||
#define C0_STATUS_CU0_SHF S_StatusCU1
|
||||
#define C0_STATUS_CU0_MSK M_StatusCU1
|
||||
#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
|
||||
|
||||
#define C0_STATUS_RP_SHF S_StatusRP
|
||||
#define C0_STATUS_RP_MSK M_StatusRP
|
||||
#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
|
||||
|
||||
#define C0_STATUS_FR_SHF S_StatusFR
|
||||
#define C0_STATUS_FR_MSK M_StatusFR
|
||||
#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
|
||||
|
||||
#define C0_STATUS_RE_SHF S_StatusRE
|
||||
#define C0_STATUS_RE_MSK M_StatusRE
|
||||
#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
|
||||
|
||||
#define C0_STATUS_BEV_SHF S_StatusBEV
|
||||
#define C0_STATUS_BEV_MSK M_StatusBEV
|
||||
#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
|
||||
|
||||
#define C0_STATUS_TS_SHF S_StatusTS
|
||||
#define C0_STATUS_TS_MSK M_StatusTS
|
||||
#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
|
||||
|
||||
#define C0_STATUS_SR_SHF S_StatusSR
|
||||
#define C0_STATUS_SR_MSK M_StatusSR
|
||||
#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
|
||||
|
||||
#define C0_STATUS_NMI_SHF S_StatusNMI
|
||||
#define C0_STATUS_NMI_MSK M_StatusNMI
|
||||
#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
|
||||
|
||||
#define C0_STATUS_IM_SHF S_StatusIM
|
||||
#define C0_STATUS_IM_MSK M_StatusIM
|
||||
/* Note that the the definitions below indicate the interrupt number
|
||||
* rather than the mask.
|
||||
* (0..1 for SW interrupts and 2...7 for HW interrupts)
|
||||
*/
|
||||
#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
|
||||
#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
|
||||
#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
|
||||
|
||||
/* Max interrupt code */
|
||||
#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
|
||||
|
||||
#define C0_STATUS_KSU_SHF S_StatusKSU
|
||||
#define C0_STATUS_KSU_MSK M_StatusKSU
|
||||
|
||||
#define C0_STATUS_UM_SHF S_StatusUM
|
||||
#define C0_STATUS_UM_MSK M_StatusUM
|
||||
#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
|
||||
|
||||
#define C0_STATUS_ERL_SHF S_StatusERL
|
||||
#define C0_STATUS_ERL_MSK M_StatusERL
|
||||
#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
|
||||
|
||||
#define C0_STATUS_EXL_SHF S_StatusEXL
|
||||
#define C0_STATUS_EXL_MSK M_StatusEXL
|
||||
#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
|
||||
|
||||
#define C0_STATUS_IE_SHF S_StatusIE
|
||||
#define C0_STATUS_IE_MSK M_StatusIE
|
||||
#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
|
||||
|
||||
|
||||
/* C0_PRID register encoding */
|
||||
|
||||
#define C0_PRID_OPT_SHF S_PRIdCoOpt
|
||||
#define C0_PRID_OPT_MSK M_PRIdCoOpt
|
||||
|
||||
#define C0_PRID_COMP_SHF S_PRIdCoID
|
||||
#define C0_PRID_COMP_MSK M_PRIdCoID
|
||||
#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
|
||||
#define C0_PRID_COMP_NOT_MIPS32_64 0
|
||||
|
||||
#define C0_PRID_PRID_SHF S_PRIdImp
|
||||
#define C0_PRID_PRID_MSK M_PRIdImp
|
||||
|
||||
/* Jade */
|
||||
#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
|
||||
#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
|
||||
/* Emerald */
|
||||
#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
|
||||
#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
|
||||
/* Coral */
|
||||
#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
|
||||
/* Opal */
|
||||
#define C0_PRID_PRID_5K K_PRIdImp_Opal
|
||||
/* Ruby */
|
||||
#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
|
||||
/* Other CPUs */
|
||||
#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
|
||||
#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
|
||||
#define C0_PRID_PRID_RM70XX 0x27
|
||||
|
||||
#define C0_PRID_REV_SHF S_PRIdRev
|
||||
#define C0_PRID_REV_MSK M_PRIdRev
|
||||
|
||||
|
||||
#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4Kc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4Kmp << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4KEc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4KEmp << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4KSc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_5K << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_20Kc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_RM52XX << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_RM70XX << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
/* C0_ENTRYHI register encoding */
|
||||
|
||||
#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
|
||||
#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
|
||||
|
||||
#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
|
||||
#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
|
||||
|
||||
|
||||
/* C0_CAUSE register encoding */
|
||||
|
||||
#define C0_CAUSE_BD_SHF S_CauseBD
|
||||
#define C0_CAUSE_BD_MSK M_CauseBD
|
||||
#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
|
||||
|
||||
#define C0_CAUSE_CE_SHF S_CauseCE
|
||||
#define C0_CAUSE_CE_MSK M_CauseCE
|
||||
|
||||
#define C0_CAUSE_IV_SHF S_CauseIV
|
||||
#define C0_CAUSE_IV_MSK M_CauseIV
|
||||
#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
|
||||
|
||||
#define C0_CAUSE_WP_SHF S_CauseWP
|
||||
#define C0_CAUSE_WP_MSK M_CauseWP
|
||||
#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
|
||||
|
||||
#define C0_CAUSE_IP_SHF S_CauseIP
|
||||
#define C0_CAUSE_IP_MSK M_CauseIP
|
||||
|
||||
#define C0_CAUSE_CODE_SHF S_CauseExcCode
|
||||
#define C0_CAUSE_CODE_MSK M_CauseExcCode
|
||||
|
||||
#define C0_CAUSE_CODE_INT EX_INT
|
||||
#define C0_CAUSE_CODE_MOD EX_MOD
|
||||
#define C0_CAUSE_CODE_TLBL EX_TLBL
|
||||
#define C0_CAUSE_CODE_TLBS EX_TLBS
|
||||
#define C0_CAUSE_CODE_ADEL EX_ADEL
|
||||
#define C0_CAUSE_CODE_ADES EX_ADES
|
||||
#define C0_CAUSE_CODE_IBE EX_IBE
|
||||
#define C0_CAUSE_CODE_DBE EX_DBE
|
||||
#define C0_CAUSE_CODE_SYS EX_SYS
|
||||
#define C0_CAUSE_CODE_BP EX_BP
|
||||
#define C0_CAUSE_CODE_RI EX_RI
|
||||
#define C0_CAUSE_CODE_CPU EX_CPU
|
||||
#define C0_CAUSE_CODE_OV EX_OV
|
||||
#define C0_CAUSE_CODE_TR EV_TR
|
||||
#define C0_CAUSE_CODE_FPE EX_FPE
|
||||
#define C0_CAUSE_CODE_WATCH EX_WATCH
|
||||
#define C0_CAUSE_CODE_MCHECK EX_MCHECK
|
||||
|
||||
/* Max cause code */
|
||||
#define C0_CAUSE_CODE_MAX EX_MCHECK
|
||||
|
||||
|
||||
/* C0_PAGEMASK register encoding */
|
||||
#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
|
||||
#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
|
||||
#define C0_PAGEMASK_MASK_4K K_PageMask4K
|
||||
#define C0_PAGEMASK_MASK_16K K_PageMask16K
|
||||
#define C0_PAGEMASK_MASK_64K K_PageMask64K
|
||||
#define C0_PAGEMASK_MASK_256K K_PageMask256K
|
||||
#define C0_PAGEMASK_MASK_1M K_PageMask1M
|
||||
#define C0_PAGEMASK_MASK_4M K_PageMask4M
|
||||
#define C0_PAGEMASK_MASK_16M K_PageMask16M
|
||||
|
||||
|
||||
/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
|
||||
#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
|
||||
#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
|
||||
|
||||
#define C0_ENTRYLO0_C_SHF S_EntryLoC
|
||||
#define C0_ENTRYLO0_C_MSK M_EntryLoC
|
||||
|
||||
#define C0_ENTRYLO0_D_SHF S_EntryLoD
|
||||
#define C0_ENTRYLO0_D_MSK M_EntryLoD
|
||||
|
||||
#define C0_ENTRYLO0_V_SHF S_EntryLoV
|
||||
#define C0_ENTRYLO0_V_MSK M_EntryLoV
|
||||
|
||||
#define C0_ENTRYLO0_G_SHF S_EntryLoG
|
||||
#define C0_ENTRYLO0_G_MSK M_EntryLoG
|
||||
|
||||
|
||||
/* FPU (CP1) FIR register encoding */
|
||||
#define C1_FIR_3D_SHF S_FIRConfig3D
|
||||
#define C1_FIR_3D_MSK M_FIRConfig3D
|
||||
|
||||
#define C1_FIR_PS_SHF S_FIRConfigPS
|
||||
#define C1_FIR_PS_MSK M_FIRConfigPS
|
||||
|
||||
#define C1_FIR_D_SHF S_FIRConfigD
|
||||
#define C1_FIR_D_MSK M_FIRConfigD
|
||||
|
||||
#define C1_FIR_S_SHF S_FIRConfigS
|
||||
#define C1_FIR_S_MSK M_FIRConfigS
|
||||
|
||||
#define C1_FIR_PRID_SHF S_FIRImp
|
||||
#define C1_FIR_PRID_MSK M_FIRImp
|
||||
|
||||
#define C1_FIR_REV_SHF S_FIRRev
|
||||
#define C1_FIR_REV_MSK M_FIRRev
|
||||
|
||||
|
||||
/* FPU (CP1) FCSR control/status register */
|
||||
#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
|
||||
#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
|
||||
|
||||
#define C1_FCSR_FS_SHF S_FCSRFS
|
||||
#define C1_FCSR_FS_MSK M_FCSRFS
|
||||
#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
|
||||
|
||||
#define C1_FCSR_CC_SHF S_FCSRCC
|
||||
#define C1_FCSR_CC_MSK M_FCSRCC
|
||||
|
||||
#define C1_FCSR_IMPL_SHF S_FCSRImpl
|
||||
#define C1_FCSR_IMPL_MSK M_FCSRImpl
|
||||
|
||||
#define C1_FCSR_EXC_SHF S_FCSRExc
|
||||
#define C1_FCSR_EXC_MSK M_FCSRExc
|
||||
|
||||
#define C1_FCSR_ENA_SHF S_FCSREna
|
||||
#define C1_FCSR_ENA_MSK M_FCSREna
|
||||
|
||||
#define C1_FCSR_FLG_SHF S_FCSRFlg
|
||||
#define C1_FCSR_FLG_MSK M_FCSRFlg
|
||||
|
||||
#define C1_FCSR_RM_SHF S_FCSRRM
|
||||
#define C1_FCSR_RM_MSK M_FCSRRM
|
||||
#define C1_FCSR_RM_RN K_FCSRRM_RN
|
||||
#define C1_FCSR_RM_RZ K_FCSRRM_RZ
|
||||
#define C1_FCSR_RM_RP K_FCSRRM_RP
|
||||
#define C1_FCSR_RM_RM K_FCSRRM_RM
|
||||
|
||||
|
||||
|
||||
/* cache operations */
|
||||
|
||||
#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
|
||||
|
||||
#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
|
||||
#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
|
||||
#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
|
||||
#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
|
||||
#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
|
||||
#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
|
||||
#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
|
||||
|
||||
#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
|
||||
#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
|
||||
#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
|
||||
#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
|
||||
#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
|
||||
#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
|
||||
#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
|
||||
|
||||
#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
|
||||
|
||||
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||
* processors. Only relevant in early engineering samples of test
|
||||
* chips (RTL revision <= 3.0).
|
||||
*
|
||||
* The bug is described in :
|
||||
*
|
||||
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||
* MIPS Document No: MD00003
|
||||
*
|
||||
* The bug is identified as : C16
|
||||
*/
|
||||
#ifndef SET_MIPS0
|
||||
#define SET_MIPS0()
|
||||
#define SET_PUSH()
|
||||
#define SET_POP()
|
||||
#endif
|
||||
#define ICACHE_INVALIDATE_WORKAROUND(reg) \
|
||||
SET_PUSH(); \
|
||||
SET_MIPS0(); \
|
||||
la reg, 999f; \
|
||||
SET_POP(); \
|
||||
cache ICACHE_ADDR_FILL, 0(reg); \
|
||||
sync; \
|
||||
nop; nop; nop; nop; \
|
||||
999:
|
||||
|
||||
/* EMPTY_PIPELINE is used for the below cache invalidation operations.
|
||||
* When $I is invalidated, there will still be operations in the
|
||||
* pipeline. We make sure these are 'nop' operations.
|
||||
*/
|
||||
#define EMPTY_PIPELINE nop; nop; nop; nop
|
||||
|
||||
#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
|
||||
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||
cache ICACHE_INDEX_INVALIDATE, 0(index); \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
|
||||
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||
cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
/* The sync used in the below macro is there in case we are installing
|
||||
* a new instruction (flush $D, sync, invalidate $I sequence).
|
||||
*/
|
||||
#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
|
||||
cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
|
||||
sync; \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
/* Config1 cache field decoding */
|
||||
#define CACHE_CALC_SPW(s) ( 64 << (s) )
|
||||
#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
|
||||
#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
|
||||
#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
|
||||
|
||||
|
||||
/**** Move from/to Coprocessor operations ****/
|
||||
|
||||
/* We use ssnop instead of nop operations in order to handle
|
||||
* superscalar CPUs.
|
||||
* The "sll zero,zero,1" notation is compiler backwards compatible.
|
||||
*/
|
||||
#define SSNOP sll zero,zero,1
|
||||
#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
|
||||
|
||||
#define MFLO(dst) \
|
||||
mflo dst;\
|
||||
NOPS
|
||||
|
||||
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||
* processors.
|
||||
*
|
||||
* This concerns the nop instruction before mtc0 in the
|
||||
* MTC0 macro below.
|
||||
*
|
||||
* The bug is described in :
|
||||
*
|
||||
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||
* MIPS Document No: MD00003
|
||||
*
|
||||
* The bug is identified as : C27
|
||||
*/
|
||||
|
||||
#define MTC0(src, dst) \
|
||||
nop; \
|
||||
mtc0 src,dst;\
|
||||
NOPS
|
||||
|
||||
#define DMTC0(src, dst) \
|
||||
nop; \
|
||||
dmtc0 src,dst;\
|
||||
NOPS
|
||||
|
||||
#define MFC0(dst, src) \
|
||||
mfc0 dst,src;\
|
||||
NOPS
|
||||
|
||||
#define DMFC0(dst, src) \
|
||||
dmfc0 dst,src;\
|
||||
NOPS
|
||||
|
||||
#define MFC0_SEL_OPCODE(dst, src, sel)\
|
||||
.##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||
NOPS
|
||||
|
||||
#define MTC0_SEL_OPCODE(dst, src, sel)\
|
||||
.##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||
NOPS
|
||||
|
||||
#define LDC1(dst, src, offs)\
|
||||
.##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
|
||||
|
||||
#define SDC1(src, dst, offs)\
|
||||
.##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
|
||||
|
||||
|
||||
/* Instruction opcode fields */
|
||||
#define OPC_SPECIAL 0x0
|
||||
#define OPC_REGIM 0x1
|
||||
#define OPC_J 0x2
|
||||
#define OPC_JAL 0x3
|
||||
#define OPC_BEQ 0x4
|
||||
#define OPC_BNE 0x5
|
||||
#define OPC_BLEZ 0x6
|
||||
#define OPC_BGTZ 0x7
|
||||
#define OPC_COP1 0x11
|
||||
#define OPC_JALX 0x1D
|
||||
#define OPC_BEQL 0x14
|
||||
#define OPC_BNEL 0x15
|
||||
#define OPC_BLEZL 0x16
|
||||
#define OPC_BGTZL 0x17
|
||||
|
||||
/* Instruction function fields */
|
||||
#define FUNC_JR 0x8
|
||||
#define FUNC_JALR 0x9
|
||||
|
||||
/* Instruction rt fields */
|
||||
#define RT_BLTZ 0x0
|
||||
#define RT_BGEZ 0x1
|
||||
#define RT_BLTZL 0x2
|
||||
#define RT_BGEZL 0x3
|
||||
#define RT_BLTZAL 0x10
|
||||
#define RT_BGEZAL 0x11
|
||||
#define RT_BLTZALL 0x12
|
||||
#define RT_BGEZALL 0x13
|
||||
|
||||
/* Instruction rs fields */
|
||||
#define RS_BC1 0x08
|
||||
|
||||
/* Access macros for instruction fields */
|
||||
#define MIPS_OPCODE( instr) ((instr) >> 26)
|
||||
#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
|
||||
#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
|
||||
#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
|
||||
#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
|
||||
#define MIPS_TARGET(instr) ((instr) & MSK(26))
|
||||
|
||||
/* Instructions */
|
||||
#define OPCODE_DERET 0x4200001f
|
||||
#define OPCODE_BREAK 0x0005000d
|
||||
#define OPCODE_NOP 0
|
||||
#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
|
||||
|
||||
#define DERET .##word OPCODE_DERET
|
||||
|
||||
/* MIPS16e opcodes and instruction field access macros */
|
||||
|
||||
#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
|
||||
#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
|
||||
#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
|
||||
#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
|
||||
#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
|
||||
#define MIPS16E_OPC_EXTEND 0x1e
|
||||
#define MIPS16E_OPC_JAL_X 0x03
|
||||
#define MIPS16E_OPC_B 0x02
|
||||
#define MIPS16E_OPC_BEQZ 0x04
|
||||
#define MIPS16E_OPC_BNEZ 0x05
|
||||
#define MIPS16E_OPC_I8 0x0c
|
||||
#define MIPS16E_I8_FUNC_BTEQZ 0x00
|
||||
#define MIPS16E_I8_FUNC_BTNEZ 0x01
|
||||
#define MIPS16E_X_JALX 0x01
|
||||
#define MIPS16E_OPC_RR 0x1d
|
||||
#define MIPS16E_RR_FUNC_JALRC 0x00
|
||||
#define MIPS16E_RR_RY_JRRX 0x00
|
||||
#define MIPS16E_RR_RY_JRRA 0x01
|
||||
#define MIPS16E_RR_RY_JALR 0x02
|
||||
#define MIPS16E_RR_RY_JRCRX 0x04
|
||||
#define MIPS16E_RR_RY_JRCRA 0x05
|
||||
#define MIPS16E_RR_RY_JALRC 0x06
|
||||
|
||||
#define MIPS16E_OPCODE_BREAK 0xE805
|
||||
#define MIPS16E_OPCODE_NOP 0x6500
|
||||
|
||||
/* MIPS reset vector */
|
||||
#define MIPS_RESET_VECTOR 0x1fc00000
|
||||
|
||||
/* Clock periods per count register increment */
|
||||
#define MIPS4K_COUNT_CLK_PER_CYCLE 2
|
||||
#define MIPS5K_COUNT_CLK_PER_CYCLE 2
|
||||
#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
|
||||
|
||||
|
||||
/**** MIPS 4K/5K families specific fields of CONFIG register ****/
|
||||
|
||||
#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23
|
||||
#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF)
|
||||
|
||||
#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU
|
||||
#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF)
|
||||
|
||||
|
||||
/**** MIPS 20Kc specific fields of CONFIG register ****/
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_EC_SHF 28
|
||||
#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_DD_SHF 27
|
||||
#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_LP_SHF 26
|
||||
#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_SP_SHF 25
|
||||
#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_TI_SHF 24
|
||||
#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Interface function definition */
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
|
||||
#endif /* #ifndef __MIPS_H__ */
|
||||
985
firmware/export/mipsregs.h
Executable file
985
firmware/export/mipsregs.h
Executable file
|
|
@ -0,0 +1,985 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
|
||||
* Copyright (C) 2000 Silicon Graphics, Inc.
|
||||
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
|
||||
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2003 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef _ASM_MIPSREGS_H
|
||||
#define _ASM_MIPSREGS_H
|
||||
|
||||
//#include <linux/config.h>
|
||||
//#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* The following macros are especially useful for __asm__
|
||||
* inline assembler.
|
||||
*/
|
||||
#ifndef __STR
|
||||
#define __STR(x) #x
|
||||
#endif
|
||||
#ifndef STR
|
||||
#define STR(x) __STR(x)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Configure language
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ULCAST_
|
||||
#else
|
||||
#define _ULCAST_ (unsigned long)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Coprocessor 0 register names
|
||||
*/
|
||||
#define CP0_INDEX $0
|
||||
#define CP0_RANDOM $1
|
||||
#define CP0_ENTRYLO0 $2
|
||||
#define CP0_ENTRYLO1 $3
|
||||
#define CP0_CONF $3
|
||||
#define CP0_CONTEXT $4
|
||||
#define CP0_PAGEMASK $5
|
||||
#define CP0_WIRED $6
|
||||
#define CP0_INFO $7
|
||||
#define CP0_BADVADDR $8
|
||||
#define CP0_COUNT $9
|
||||
#define CP0_ENTRYHI $10
|
||||
#define CP0_COMPARE $11
|
||||
#define CP0_STATUS $12
|
||||
#define CP0_CAUSE $13
|
||||
#define CP0_EPC $14
|
||||
#define CP0_PRID $15
|
||||
#define CP0_CONFIG $16
|
||||
#define CP0_LLADDR $17
|
||||
#define CP0_WATCHLO $18
|
||||
#define CP0_WATCHHI $19
|
||||
#define CP0_XCONTEXT $20
|
||||
#define CP0_FRAMEMASK $21
|
||||
#define CP0_DIAGNOSTIC $22
|
||||
#define CP0_DEBUG $23
|
||||
#define CP0_DEPC $24
|
||||
#define CP0_PERFORMANCE $25
|
||||
#define CP0_ECC $26
|
||||
#define CP0_CACHEERR $27
|
||||
#define CP0_TAGLO $28
|
||||
#define CP0_TAGHI $29
|
||||
#define CP0_ERROREPC $30
|
||||
#define CP0_DESAVE $31
|
||||
|
||||
/*
|
||||
* R4640/R4650 cp0 register names. These registers are listed
|
||||
* here only for completeness; without MMU these CPUs are not useable
|
||||
* by Linux. A future ELKS port might take make Linux run on them
|
||||
* though ...
|
||||
*/
|
||||
#define CP0_IBASE $0
|
||||
#define CP0_IBOUND $1
|
||||
#define CP0_DBASE $2
|
||||
#define CP0_DBOUND $3
|
||||
#define CP0_CALG $17
|
||||
#define CP0_IWATCH $18
|
||||
#define CP0_DWATCH $19
|
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 1 register names
|
||||
*/
|
||||
#define CP0_S1_DERRADDR0 $26
|
||||
#define CP0_S1_DERRADDR1 $27
|
||||
#define CP0_S1_INTCONTROL $20
|
||||
|
||||
/*
|
||||
* TX39 Series
|
||||
*/
|
||||
#define CP0_TX39_CACHE $7
|
||||
|
||||
/*
|
||||
* Coprocessor 1 (FPU) register names
|
||||
*/
|
||||
#define CP1_REVISION $0
|
||||
#define CP1_STATUS $31
|
||||
|
||||
/*
|
||||
* FPU Status Register Values
|
||||
*/
|
||||
/*
|
||||
* Status Register Values
|
||||
*/
|
||||
|
||||
#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
|
||||
#define FPU_CSR_COND 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
|
||||
#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
|
||||
#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
|
||||
#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
|
||||
#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
|
||||
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
|
||||
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
|
||||
|
||||
/*
|
||||
* X the exception cause indicator
|
||||
* E the exception enable
|
||||
* S the sticky/flag bit
|
||||
*/
|
||||
#define FPU_CSR_ALL_X 0x0003f000
|
||||
#define FPU_CSR_UNI_X 0x00020000
|
||||
#define FPU_CSR_INV_X 0x00010000
|
||||
#define FPU_CSR_DIV_X 0x00008000
|
||||
#define FPU_CSR_OVF_X 0x00004000
|
||||
#define FPU_CSR_UDF_X 0x00002000
|
||||
#define FPU_CSR_INE_X 0x00001000
|
||||
|
||||
#define FPU_CSR_ALL_E 0x00000f80
|
||||
#define FPU_CSR_INV_E 0x00000800
|
||||
#define FPU_CSR_DIV_E 0x00000400
|
||||
#define FPU_CSR_OVF_E 0x00000200
|
||||
#define FPU_CSR_UDF_E 0x00000100
|
||||
#define FPU_CSR_INE_E 0x00000080
|
||||
|
||||
#define FPU_CSR_ALL_S 0x0000007c
|
||||
#define FPU_CSR_INV_S 0x00000040
|
||||
#define FPU_CSR_DIV_S 0x00000020
|
||||
#define FPU_CSR_OVF_S 0x00000010
|
||||
#define FPU_CSR_UDF_S 0x00000008
|
||||
#define FPU_CSR_INE_S 0x00000004
|
||||
|
||||
/* rounding mode */
|
||||
#define FPU_CSR_RN 0x0 /* nearest */
|
||||
#define FPU_CSR_RZ 0x1 /* towards zero */
|
||||
#define FPU_CSR_RU 0x2 /* towards +Infinity */
|
||||
#define FPU_CSR_RD 0x3 /* towards -Infinity */
|
||||
|
||||
|
||||
/*
|
||||
* Values for PageMask register
|
||||
*/
|
||||
#ifdef CONFIG_CPU_VR41XX
|
||||
|
||||
/* Why doesn't stupidity hurt ... */
|
||||
|
||||
#define PM_1K 0x00000000
|
||||
#define PM_4K 0x00001800
|
||||
#define PM_16K 0x00007800
|
||||
#define PM_64K 0x0001f800
|
||||
#define PM_256K 0x0007f800
|
||||
|
||||
#else
|
||||
|
||||
#define PM_4K 0x00000000
|
||||
#define PM_16K 0x00006000
|
||||
#define PM_64K 0x0001e000
|
||||
#define PM_256K 0x0007e000
|
||||
#define PM_1M 0x001fe000
|
||||
#define PM_4M 0x007fe000
|
||||
#define PM_16M 0x01ffe000
|
||||
#define PM_64M 0x07ffe000
|
||||
#define PM_256M 0x1fffe000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values used for computation of new tlb entries
|
||||
*/
|
||||
#define PL_4K 12
|
||||
#define PL_16K 14
|
||||
#define PL_64K 16
|
||||
#define PL_256K 18
|
||||
#define PL_1M 20
|
||||
#define PL_4M 22
|
||||
#define PL_16M 24
|
||||
#define PL_64M 26
|
||||
#define PL_256M 28
|
||||
|
||||
/*
|
||||
* R4x00 interrupt enable / cause bits
|
||||
*/
|
||||
#define IE_SW0 (_ULCAST_(1) << 8)
|
||||
#define IE_SW1 (_ULCAST_(1) << 9)
|
||||
#define IE_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define IE_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define IE_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define IE_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define IE_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define IE_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* R4x00 interrupt cause bits
|
||||
*/
|
||||
#define C_SW0 (_ULCAST_(1) << 8)
|
||||
#define C_SW1 (_ULCAST_(1) << 9)
|
||||
#define C_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define C_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define C_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define C_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define C_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define C_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* Bitfields in the R4xx0 cp0 status register
|
||||
*/
|
||||
#define ST0_IE 0x00000001
|
||||
#define ST0_EXL 0x00000002
|
||||
#define ST0_ERL 0x00000004
|
||||
#define ST0_KSU 0x00000018
|
||||
# define KSU_USER 0x00000010
|
||||
# define KSU_SUPERVISOR 0x00000008
|
||||
# define KSU_KERNEL 0x00000000
|
||||
#define ST0_UX 0x00000020
|
||||
#define ST0_SX 0x00000040
|
||||
#define ST0_KX 0x00000080
|
||||
#define ST0_DE 0x00010000
|
||||
#define ST0_CE 0x00020000
|
||||
|
||||
/*
|
||||
* Bitfields in the R[23]000 cp0 status register.
|
||||
*/
|
||||
#define ST0_IEC 0x00000001
|
||||
#define ST0_KUC 0x00000002
|
||||
#define ST0_IEP 0x00000004
|
||||
#define ST0_KUP 0x00000008
|
||||
#define ST0_IEO 0x00000010
|
||||
#define ST0_KUO 0x00000020
|
||||
/* bits 6 & 7 are reserved on R[23]000 */
|
||||
#define ST0_ISC 0x00010000
|
||||
#define ST0_SWC 0x00020000
|
||||
#define ST0_CM 0x00080000
|
||||
|
||||
/*
|
||||
* Bits specific to the R4640/R4650
|
||||
*/
|
||||
#define ST0_UM (_ULCAST_(1) << 4)
|
||||
#define ST0_IL (_ULCAST_(1) << 23)
|
||||
#define ST0_DL (_ULCAST_(1) << 24)
|
||||
|
||||
/*
|
||||
* Bitfields in the TX39 family CP0 Configuration Register 3
|
||||
*/
|
||||
#define TX39_CONF_ICS_SHIFT 19
|
||||
#define TX39_CONF_ICS_MASK 0x00380000
|
||||
#define TX39_CONF_ICS_1KB 0x00000000
|
||||
#define TX39_CONF_ICS_2KB 0x00080000
|
||||
#define TX39_CONF_ICS_4KB 0x00100000
|
||||
#define TX39_CONF_ICS_8KB 0x00180000
|
||||
#define TX39_CONF_ICS_16KB 0x00200000
|
||||
|
||||
#define TX39_CONF_DCS_SHIFT 16
|
||||
#define TX39_CONF_DCS_MASK 0x00070000
|
||||
#define TX39_CONF_DCS_1KB 0x00000000
|
||||
#define TX39_CONF_DCS_2KB 0x00010000
|
||||
#define TX39_CONF_DCS_4KB 0x00020000
|
||||
#define TX39_CONF_DCS_8KB 0x00030000
|
||||
#define TX39_CONF_DCS_16KB 0x00040000
|
||||
|
||||
#define TX39_CONF_CWFON 0x00004000
|
||||
#define TX39_CONF_WBON 0x00002000
|
||||
#define TX39_CONF_RF_SHIFT 10
|
||||
#define TX39_CONF_RF_MASK 0x00000c00
|
||||
#define TX39_CONF_DOZE 0x00000200
|
||||
#define TX39_CONF_HALT 0x00000100
|
||||
#define TX39_CONF_LOCK 0x00000080
|
||||
#define TX39_CONF_ICE 0x00000020
|
||||
#define TX39_CONF_DCE 0x00000010
|
||||
#define TX39_CONF_IRSIZE_SHIFT 2
|
||||
#define TX39_CONF_IRSIZE_MASK 0x0000000c
|
||||
#define TX39_CONF_DRSIZE_SHIFT 0
|
||||
#define TX39_CONF_DRSIZE_MASK 0x00000003
|
||||
|
||||
/*
|
||||
* Status register bits available in all MIPS CPUs.
|
||||
*/
|
||||
#define ST0_IM 0x0000ff00
|
||||
#define STATUSB_IP0 8
|
||||
#define STATUSF_IP0 (_ULCAST_(1) << 8)
|
||||
#define STATUSB_IP1 9
|
||||
#define STATUSF_IP1 (_ULCAST_(1) << 9)
|
||||
#define STATUSB_IP2 10
|
||||
#define STATUSF_IP2 (_ULCAST_(1) << 10)
|
||||
#define STATUSB_IP3 11
|
||||
#define STATUSF_IP3 (_ULCAST_(1) << 11)
|
||||
#define STATUSB_IP4 12
|
||||
#define STATUSF_IP4 (_ULCAST_(1) << 12)
|
||||
#define STATUSB_IP5 13
|
||||
#define STATUSF_IP5 (_ULCAST_(1) << 13)
|
||||
#define STATUSB_IP6 14
|
||||
#define STATUSF_IP6 (_ULCAST_(1) << 14)
|
||||
#define STATUSB_IP7 15
|
||||
#define STATUSF_IP7 (_ULCAST_(1) << 15)
|
||||
#define STATUSB_IP8 0
|
||||
#define STATUSF_IP8 (_ULCAST_(1) << 0)
|
||||
#define STATUSB_IP9 1
|
||||
#define STATUSF_IP9 (_ULCAST_(1) << 1)
|
||||
#define STATUSB_IP10 2
|
||||
#define STATUSF_IP10 (_ULCAST_(1) << 2)
|
||||
#define STATUSB_IP11 3
|
||||
#define STATUSF_IP11 (_ULCAST_(1) << 3)
|
||||
#define STATUSB_IP12 4
|
||||
#define STATUSF_IP12 (_ULCAST_(1) << 4)
|
||||
#define STATUSB_IP13 5
|
||||
#define STATUSF_IP13 (_ULCAST_(1) << 5)
|
||||
#define STATUSB_IP14 6
|
||||
#define STATUSF_IP14 (_ULCAST_(1) << 6)
|
||||
#define STATUSB_IP15 7
|
||||
#define STATUSF_IP15 (_ULCAST_(1) << 7)
|
||||
#define ST0_CH 0x00040000
|
||||
#define ST0_SR 0x00100000
|
||||
#define ST0_TS 0x00200000
|
||||
#define ST0_BEV 0x00400000
|
||||
#define ST0_RE 0x02000000
|
||||
#define ST0_FR 0x04000000
|
||||
#define ST0_CU 0xf0000000
|
||||
#define ST0_CU0 0x10000000
|
||||
#define ST0_CU1 0x20000000
|
||||
#define ST0_CU2 0x40000000
|
||||
#define ST0_CU3 0x80000000
|
||||
#define ST0_XX 0x80000000 /* MIPS IV naming */
|
||||
|
||||
/*
|
||||
* Bitfields and bit numbers in the coprocessor 0 cause register.
|
||||
*
|
||||
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
|
||||
*/
|
||||
#define CAUSEB_EXCCODE 2
|
||||
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
|
||||
#define CAUSEB_IP 8
|
||||
#define CAUSEF_IP (_ULCAST_(255) << 8)
|
||||
#define CAUSEB_IP0 8
|
||||
#define CAUSEF_IP0 (_ULCAST_(1) << 8)
|
||||
#define CAUSEB_IP1 9
|
||||
#define CAUSEF_IP1 (_ULCAST_(1) << 9)
|
||||
#define CAUSEB_IP2 10
|
||||
#define CAUSEF_IP2 (_ULCAST_(1) << 10)
|
||||
#define CAUSEB_IP3 11
|
||||
#define CAUSEF_IP3 (_ULCAST_(1) << 11)
|
||||
#define CAUSEB_IP4 12
|
||||
#define CAUSEF_IP4 (_ULCAST_(1) << 12)
|
||||
#define CAUSEB_IP5 13
|
||||
#define CAUSEF_IP5 (_ULCAST_(1) << 13)
|
||||
#define CAUSEB_IP6 14
|
||||
#define CAUSEF_IP6 (_ULCAST_(1) << 14)
|
||||
#define CAUSEB_IP7 15
|
||||
#define CAUSEF_IP7 (_ULCAST_(1) << 15)
|
||||
#define CAUSEB_IV 23
|
||||
#define CAUSEF_IV (_ULCAST_(1) << 23)
|
||||
#define CAUSEB_CE 28
|
||||
#define CAUSEF_CE (_ULCAST_(3) << 28)
|
||||
#define CAUSEB_BD 31
|
||||
#define CAUSEF_BD (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* Bits in the coprocessor 0 config register.
|
||||
*/
|
||||
/* Generic bits. */
|
||||
#define CONF_CM_CACHABLE_NO_WA 0
|
||||
#define CONF_CM_CACHABLE_WA 1
|
||||
#define CONF_CM_UNCACHED 2
|
||||
#define CONF_CM_CACHABLE_NONCOHERENT 3
|
||||
#define CONF_CM_CACHABLE_CE 4
|
||||
#define CONF_CM_CACHABLE_COW 5
|
||||
#define CONF_CM_CACHABLE_CUW 6
|
||||
#define CONF_CM_CACHABLE_ACCELERATED 7
|
||||
#define CONF_CM_CMASK 7
|
||||
#define CONF_BE (_ULCAST_(1) << 15)
|
||||
|
||||
/* Bits common to various processors. */
|
||||
#define CONF_CU (_ULCAST_(1) << 3)
|
||||
#define CONF_DB (_ULCAST_(1) << 4)
|
||||
#define CONF_IB (_ULCAST_(1) << 5)
|
||||
#define CONF_DC (_ULCAST_(7) << 6)
|
||||
#define CONF_IC (_ULCAST_(7) << 9)
|
||||
#define CONF_EB (_ULCAST_(1) << 13)
|
||||
#define CONF_EM (_ULCAST_(1) << 14)
|
||||
#define CONF_SM (_ULCAST_(1) << 16)
|
||||
#define CONF_SC (_ULCAST_(1) << 17)
|
||||
#define CONF_EW (_ULCAST_(3) << 18)
|
||||
#define CONF_EP (_ULCAST_(15)<< 24)
|
||||
#define CONF_EC (_ULCAST_(7) << 28)
|
||||
#define CONF_CM (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the R4xx0. */
|
||||
#define R4K_CONF_SW (_ULCAST_(1) << 20)
|
||||
#define R4K_CONF_SS (_ULCAST_(1) << 21)
|
||||
#define R4K_CONF_SB (_ULCAST_(3) << 22)
|
||||
|
||||
/* Bits specific to the R5000. */
|
||||
#define R5K_CONF_SE (_ULCAST_(1) << 12)
|
||||
#define R5K_CONF_SS (_ULCAST_(3) << 20)
|
||||
|
||||
/* Bits specific to the R10000. */
|
||||
#define R10K_CONF_DN (_ULCAST_(3) << 3)
|
||||
#define R10K_CONF_CT (_ULCAST_(1) << 5)
|
||||
#define R10K_CONF_PE (_ULCAST_(1) << 6)
|
||||
#define R10K_CONF_PM (_ULCAST_(3) << 7)
|
||||
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
|
||||
#define R10K_CONF_SB (_ULCAST_(1) << 13)
|
||||
#define R10K_CONF_SK (_ULCAST_(1) << 14)
|
||||
#define R10K_CONF_SS (_ULCAST_(7) << 16)
|
||||
#define R10K_CONF_SC (_ULCAST_(7) << 19)
|
||||
#define R10K_CONF_DC (_ULCAST_(7) << 26)
|
||||
#define R10K_CONF_IC (_ULCAST_(7) << 29)
|
||||
|
||||
/* Bits specific to the VR41xx. */
|
||||
#define VR41_CONF_CS (_ULCAST_(1) << 12)
|
||||
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
|
||||
#define VR41_CONF_AD (_ULCAST_(1) << 23)
|
||||
|
||||
/* Bits specific to the R30xx. */
|
||||
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
|
||||
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
|
||||
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
|
||||
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
|
||||
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
|
||||
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
|
||||
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
|
||||
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
|
||||
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the TX49. */
|
||||
#define TX49_CONF_DC (_ULCAST_(1) << 16)
|
||||
#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
|
||||
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
|
||||
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
|
||||
|
||||
/* Bits specific to the MIPS32/64 PRA. */
|
||||
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
|
||||
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
|
||||
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
|
||||
#define MIPS_CONF_M (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* R10000 performance counter definitions.
|
||||
*
|
||||
* FIXME: The R10000 performance counter opens a nice way to implement CPU
|
||||
* time accounting with a precission of one cycle. I don't have
|
||||
* R10000 silicon but just a manual, so ...
|
||||
*/
|
||||
|
||||
/*
|
||||
* Events counted by counter #0
|
||||
*/
|
||||
#define CE0_CYCLES 0
|
||||
#define CE0_INSN_ISSUED 1
|
||||
#define CE0_LPSC_ISSUED 2
|
||||
#define CE0_S_ISSUED 3
|
||||
#define CE0_SC_ISSUED 4
|
||||
#define CE0_SC_FAILED 5
|
||||
#define CE0_BRANCH_DECODED 6
|
||||
#define CE0_QW_WB_SECONDARY 7
|
||||
#define CE0_CORRECTED_ECC_ERRORS 8
|
||||
#define CE0_ICACHE_MISSES 9
|
||||
#define CE0_SCACHE_I_MISSES 10
|
||||
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
|
||||
#define CE0_EXT_INTERVENTIONS_REQ 12
|
||||
#define CE0_EXT_INVALIDATE_REQ 13
|
||||
#define CE0_VIRTUAL_COHERENCY_COND 14
|
||||
#define CE0_INSN_GRADUATED 15
|
||||
|
||||
/*
|
||||
* Events counted by counter #1
|
||||
*/
|
||||
#define CE1_CYCLES 0
|
||||
#define CE1_INSN_GRADUATED 1
|
||||
#define CE1_LPSC_GRADUATED 2
|
||||
#define CE1_S_GRADUATED 3
|
||||
#define CE1_SC_GRADUATED 4
|
||||
#define CE1_FP_INSN_GRADUATED 5
|
||||
#define CE1_QW_WB_PRIMARY 6
|
||||
#define CE1_TLB_REFILL 7
|
||||
#define CE1_BRANCH_MISSPREDICTED 8
|
||||
#define CE1_DCACHE_MISS 9
|
||||
#define CE1_SCACHE_D_MISSES 10
|
||||
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
|
||||
#define CE1_EXT_INTERVENTION_HITS 12
|
||||
#define CE1_EXT_INVALIDATE_REQ 13
|
||||
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
|
||||
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
|
||||
|
||||
/*
|
||||
* These flags define in which priviledge mode the counters count events
|
||||
*/
|
||||
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
|
||||
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
|
||||
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
|
||||
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
|
||||
#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
|
||||
|
||||
/*
|
||||
* Functions to access the r10k performance counter and control registers
|
||||
*/
|
||||
#define read_r10k_perf_cntr(counter) \
|
||||
({ unsigned int __res; \
|
||||
__asm__ __volatile__( \
|
||||
"mfpc\t%0, "STR(counter) \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_r10k_perf_cntr(counter,val) \
|
||||
__asm__ __volatile__( \
|
||||
"mtpc\t%0, "STR(counter) \
|
||||
: : "r" (val));
|
||||
|
||||
#define read_r10k_perf_cntl(counter) \
|
||||
({ unsigned int __res; \
|
||||
__asm__ __volatile__( \
|
||||
"mfps\t%0, "STR(counter) \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_r10k_perf_cntl(counter,val) \
|
||||
__asm__ __volatile__( \
|
||||
"mtps\t%0, "STR(counter) \
|
||||
: : "r" (val));
|
||||
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
|
||||
#define __read_32bit_c0_register(source, sel) \
|
||||
({ int __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mfc0\t%0, " #source "\n\t" \
|
||||
: "=r" (__res)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0\n\t" \
|
||||
: "=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __read_64bit_c0_register(source, sel) \
|
||||
({ unsigned long __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmfc0\t%0, " #source "\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __write_32bit_c0_register(register, sel, value) \
|
||||
do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%z0, " #register "\n\t" \
|
||||
: : "Jr" (value)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mtc0\t%z0, " #register ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
} while (0)
|
||||
|
||||
#define __write_64bit_c0_register(register, sel, value) \
|
||||
do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmtc0\t%z0, " #register "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
} while (0)
|
||||
|
||||
#define __read_ulong_c0_register(reg, sel) \
|
||||
((sizeof(unsigned long) == 4) ? \
|
||||
__read_32bit_c0_register(reg, sel) : \
|
||||
__read_64bit_c0_register(reg, sel))
|
||||
|
||||
#define __write_ulong_c0_register(reg, sel, val) \
|
||||
do { \
|
||||
if (sizeof(unsigned long) == 4) \
|
||||
__write_32bit_c0_register(reg, sel, val); \
|
||||
else \
|
||||
__write_64bit_c0_register(reg, sel, val); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* These versions are only needed for systems with more than 38 bits of
|
||||
* physical address space running the 32-bit kernel. That's none atm :-)
|
||||
*/
|
||||
#define __read_64bit_c0_split(source, sel) \
|
||||
({ \
|
||||
unsigned long long val; \
|
||||
unsigned long flags; \
|
||||
\
|
||||
local_irq_save(flags); \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsrl\t%M0, %M0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (val)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsrl\t%M0, %M0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (val)); \
|
||||
local_irq_restore(flags); \
|
||||
\
|
||||
val; \
|
||||
})
|
||||
|
||||
#define __write_64bit_c0_split(source, sel, val) \
|
||||
do { \
|
||||
unsigned long flags; \
|
||||
\
|
||||
local_irq_save(flags); \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dsll\t%L0, %L0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
"dsll\t%M0, %M0, 32\n\t" \
|
||||
"or\t%L0, %L0, %M0\n\t" \
|
||||
"dmtc0\t%L0, " #source "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (val)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dsll\t%L0, %L0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
"dsll\t%M0, %M0, 32\n\t" \
|
||||
"or\t%L0, %L0, %M0\n\t" \
|
||||
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (val)); \
|
||||
local_irq_restore(flags); \
|
||||
} while (0)
|
||||
|
||||
#define read_c0_index() __read_32bit_c0_register($0, 0)
|
||||
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
|
||||
|
||||
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
|
||||
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
|
||||
|
||||
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
|
||||
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_conf() __read_32bit_c0_register($3, 0)
|
||||
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_context() __read_ulong_c0_register($4, 0)
|
||||
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
|
||||
|
||||
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
|
||||
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
|
||||
|
||||
#define read_c0_wired() __read_32bit_c0_register($6, 0)
|
||||
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
|
||||
|
||||
#define read_c0_info() __read_32bit_c0_register($7, 0)
|
||||
|
||||
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
|
||||
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
|
||||
|
||||
#define read_c0_count() __read_32bit_c0_register($9, 0)
|
||||
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
|
||||
|
||||
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
|
||||
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
|
||||
|
||||
#define read_c0_compare() __read_32bit_c0_register($11, 0)
|
||||
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
|
||||
|
||||
#define read_c0_status() __read_32bit_c0_register($12, 0)
|
||||
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
|
||||
|
||||
#define read_c0_cause() __read_32bit_c0_register($13, 0)
|
||||
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
|
||||
|
||||
#define read_c0_prid() __read_32bit_c0_register($15, 0)
|
||||
|
||||
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||||
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||||
#define read_c0_config2() __read_32bit_c0_register($16, 2)
|
||||
#define read_c0_config3() __read_32bit_c0_register($16, 3)
|
||||
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
|
||||
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
|
||||
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
|
||||
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
|
||||
|
||||
/*
|
||||
* The WatchLo register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
|
||||
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
|
||||
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
|
||||
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
|
||||
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
|
||||
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
|
||||
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
|
||||
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
|
||||
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
|
||||
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
|
||||
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
|
||||
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
|
||||
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
|
||||
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
|
||||
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
|
||||
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
|
||||
|
||||
/*
|
||||
* The WatchHi register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
|
||||
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
|
||||
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
|
||||
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
|
||||
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
|
||||
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
|
||||
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
|
||||
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
|
||||
|
||||
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
|
||||
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
|
||||
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
|
||||
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
|
||||
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
|
||||
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
|
||||
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
|
||||
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
|
||||
|
||||
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
|
||||
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
|
||||
|
||||
#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
|
||||
#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
|
||||
|
||||
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
|
||||
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
|
||||
|
||||
#define read_c0_debug() __read_32bit_c0_register($23, 0)
|
||||
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
|
||||
|
||||
#define read_c0_depc() __read_ulong_c0_register($24, 0)
|
||||
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
|
||||
|
||||
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
|
||||
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
|
||||
|
||||
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
|
||||
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
|
||||
|
||||
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
|
||||
|
||||
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
|
||||
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
|
||||
|
||||
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
|
||||
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
|
||||
|
||||
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
|
||||
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
|
||||
|
||||
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
|
||||
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
|
||||
|
||||
#define read_c0_epc() __read_ulong_c0_register($14, 0)
|
||||
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
|
||||
|
||||
#if 1
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
#define read_32bit_cp0_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"mfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define read_32bit_cp0_set1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
/*
|
||||
* For now use this only with interrupts disabled!
|
||||
*/
|
||||
#define read_64bit_cp0_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_32bit_cp0_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value));
|
||||
|
||||
#define write_32bit_cp0_set1_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
"ctc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value));
|
||||
|
||||
#define write_64bit_cp0_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmtc0\t%0,"STR(register)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (value))
|
||||
|
||||
/*
|
||||
* This should be changed when we get a compiler that support the MIPS32 ISA.
|
||||
*/
|
||||
#define read_mips32_cp0_config1() \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tnoreorder\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"#.set\tmips64\n\t" \
|
||||
"#mfc0\t$1, $16, 1\n\t" \
|
||||
"#.set\tmips0\n\t" \
|
||||
".word\t0x40018001\n\t" \
|
||||
"move\t%0,$1\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" \
|
||||
:"=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Macros to access the floating point coprocessor control registers
|
||||
*/
|
||||
#define read_32bit_cp1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc1\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
/* TLB operations. */
|
||||
static inline void tlb_probe(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbp\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_read(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbr\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_write_indexed(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwi\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_write_random(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwr\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
/*
|
||||
* Manipulate bits in a c0 register.
|
||||
*/
|
||||
#define __BUILD_SET_C0(name,register) \
|
||||
static inline unsigned int \
|
||||
set_c0_##name(unsigned int set) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res |= set; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
clear_c0_##name(unsigned int clear) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~clear; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
change_c0_##name(unsigned int change, unsigned int new) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~change; \
|
||||
res |= (new & change); \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
}
|
||||
|
||||
__BUILD_SET_C0(status,CP0_STATUS)
|
||||
__BUILD_SET_C0(cause,CP0_CAUSE)
|
||||
__BUILD_SET_C0(config,CP0_CONFIG)
|
||||
|
||||
#define set_cp0_status(x) set_c0_status(x)
|
||||
#define set_cp0_cause(x) set_c0_cause(x)
|
||||
#define set_cp0_config(x) set_c0_config(x)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_MIPSREGS_H */
|
||||
|
|
@ -109,6 +109,14 @@ struct regs
|
|||
uint32_t lr; /* 36 - r14 (lr) */
|
||||
uint32_t start; /* 40 - Thread start address, or NULL when started */
|
||||
};
|
||||
#elif defined(CPU_MIPS)
|
||||
struct regs
|
||||
{
|
||||
uint32_t r[27]; /* 0-104 - Registers $1, v0-v1, a0-a3, t0-t9, s0-s7, gp, fp */
|
||||
uint32_t sp; /* 108 - Stack pointer */
|
||||
uint32_t ra; /* 112 - Return address */
|
||||
uint32_t start; /* 116 - Thread start address, or NULL when started */
|
||||
};
|
||||
#endif /* CONFIG_CPU */
|
||||
#else
|
||||
struct regs
|
||||
|
|
|
|||
40
firmware/target/mips/ingenic_jz47xx/ata-jz4740.c
Executable file
40
firmware/target/mips/ingenic_jz47xx/ata-jz4740.c
Executable file
|
|
@ -0,0 +1,40 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "ata.h"
|
||||
|
||||
int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
|
||||
{
|
||||
(void)start;
|
||||
(void)count;
|
||||
(void)buf;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
|
||||
{
|
||||
(void)start;
|
||||
(void)count;
|
||||
(void)buf;
|
||||
return 0;
|
||||
}
|
||||
107
firmware/target/mips/ingenic_jz47xx/boot.lds
Executable file
107
firmware/target/mips/ingenic_jz47xx/boot.lds
Executable file
|
|
@ -0,0 +1,107 @@
|
|||
#include "config.h"
|
||||
#undef mips
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(MIPS)
|
||||
ENTRY(_start)
|
||||
STARTUP(target/mips/ingenic_jz47xx/crt0.o)
|
||||
|
||||
#define DRAMSIZE (MEMORYSIZE * 0x100000)
|
||||
|
||||
#define DRAMORIG 0x80E00000 /* HACK */
|
||||
#define IRAMORIG 0x80000000
|
||||
#define IRAMSIZE 16K
|
||||
|
||||
MEMORY
|
||||
{
|
||||
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
|
||||
IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = DRAMORIG;
|
||||
|
||||
.text : {
|
||||
loadaddress = .;
|
||||
_loadaddress = .;
|
||||
*(.init.text);
|
||||
*(.text*);
|
||||
*(.glue_7);
|
||||
*(.glue_7t);
|
||||
. = ALIGN(0x4);
|
||||
} > DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata); /* problems without this, dunno why */
|
||||
*(.rodata*);
|
||||
*(.rodata.str1.1);
|
||||
*(.rodata.str1.4);
|
||||
. = ALIGN(0x4);
|
||||
|
||||
/* Pseudo-allocate the copies of the data sections */
|
||||
_datacopy = .;
|
||||
} > DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.data : {
|
||||
*(.icode);
|
||||
*(.irodata);
|
||||
*(.idata);
|
||||
*(.data*);
|
||||
*(.scommon*);
|
||||
*(.sdata*);
|
||||
. = ALIGN(0x4);
|
||||
_dataend = . ;
|
||||
} > DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
_gp = ALIGN(16);
|
||||
.got : {
|
||||
*(.got*)
|
||||
}> DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.stack :
|
||||
{
|
||||
*(.stack)
|
||||
_stackbegin = .;
|
||||
stackbegin = .;
|
||||
. += 0x2000;
|
||||
_stackend = .;
|
||||
stackend = .;
|
||||
} > DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.bss :
|
||||
{
|
||||
_edata = .;
|
||||
*(.sbss*);
|
||||
*(.bss*);
|
||||
*(.ibss);
|
||||
*(COMMON)
|
||||
_end = .;
|
||||
} > DRAM
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.vectors IRAMORIG :
|
||||
{
|
||||
_vectorsstart = .;
|
||||
KEEP(*(.resetvectors));
|
||||
*(.resetvectors);
|
||||
KEEP(*(.vectors));
|
||||
*(.vectors);
|
||||
_vectorsend = .;
|
||||
} AT > DRAM
|
||||
_vectorscopy = LOADADDR(.vectors);
|
||||
|
||||
. = ALIGN(4);
|
||||
}
|
||||
246
firmware/target/mips/ingenic_jz47xx/crt0.S
Executable file
246
firmware/target/mips/ingenic_jz47xx/crt0.S
Executable file
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* init.S
|
||||
*
|
||||
* Initialization code for JzRISC.
|
||||
*
|
||||
* Author: Seeger Chin
|
||||
* e-mail: seeger.chin@gmail.com
|
||||
*
|
||||
* Copyright (C) 2006 Ingenic Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "config.h"
|
||||
#include "mips.h"
|
||||
|
||||
.text
|
||||
|
||||
.set mips3
|
||||
|
||||
.extern main
|
||||
|
||||
.global _start
|
||||
#ifdef BOOTLOADER
|
||||
.section .init.text,"ax",%progbits
|
||||
#else
|
||||
.section .resetvectors,"ax",%progbits
|
||||
#endif
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
#ifdef BOOTLOADER
|
||||
.word 0 /* HACK */
|
||||
.word 0 /* HACK */
|
||||
#endif
|
||||
_start:
|
||||
la ra, _start
|
||||
//----------------------------------------------------
|
||||
// init cp0 registers.
|
||||
//----------------------------------------------------
|
||||
mtc0 zero, C0_WATCHLO
|
||||
mtc0 zero, C0_WATCHHI
|
||||
|
||||
li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
|
||||
| M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
|
||||
| M_StatusIM2 | M_StatusERL)
|
||||
// BEV = Enable Boot Exception Vectors
|
||||
// IMx = Interrupt mask
|
||||
// ERL = Denotes error level
|
||||
mtc0 t0, C0_STATUS
|
||||
|
||||
li t1, M_CauseIV
|
||||
mtc0 t1, C0_CAUSE
|
||||
|
||||
//----------------------------------------------------
|
||||
// init caches, assumes a 4way*128set*32byte i/d cache
|
||||
//----------------------------------------------------
|
||||
li t0, 3 // enable cache for kseg0 accesses
|
||||
mtc0 t0, C0_CONFIG // CONFIG reg
|
||||
la t0, 0x80000000 // an idx op should use a unmappable address
|
||||
ori t1, t0, 0x4000 // 16kB cache
|
||||
mtc0 zero, C0_TAGLO // TAGLO reg
|
||||
mtc0 zero, C0_TAGHI // TAGHI reg
|
||||
|
||||
_init_cache_loop:
|
||||
cache 0x8, 0(t0) // index store icache tag
|
||||
cache 0x9, 0(t0) // index store dcache tag
|
||||
bne t0, t1, _init_cache_loop
|
||||
addiu t0, t0, 0x20 // 32 bytes per cache line
|
||||
nop
|
||||
|
||||
//----------------------------------------------------
|
||||
// Invalidate BTB
|
||||
//----------------------------------------------------
|
||||
mfc0 t0, C0_CONFIG
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, C0_CONFIG
|
||||
nop
|
||||
|
||||
//----------------------------------------------------
|
||||
// setup stack, jump to C code
|
||||
//----------------------------------------------------
|
||||
la sp, stackend
|
||||
la t0, stackbegin
|
||||
li t1, 0xDEADBEEF
|
||||
|
||||
_init_stack_loop:
|
||||
sw t1, 0(t0)
|
||||
bne t0, sp, _init_stack_loop
|
||||
addiu t0, t0, 4
|
||||
|
||||
la t0, main
|
||||
jr t0
|
||||
nop
|
||||
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
.section .vectors,"ax",%progbits
|
||||
#endif
|
||||
.extern exception_handler
|
||||
.global except_common_entry
|
||||
.type except_common_entry,@function
|
||||
except_common_entry:
|
||||
la k0, exception_handler
|
||||
jr k0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
.extern _int
|
||||
.extern _exception
|
||||
.global exception_handler
|
||||
.type exception_handler,@function
|
||||
.set noreorder
|
||||
exception_handler:
|
||||
|
||||
|
||||
addiu sp, -0x80 # Add Immediate Unsigned
|
||||
sw ra, 0(sp) # Store Word
|
||||
sw fp, 4(sp) # Store Word
|
||||
sw gp, 8(sp) # Store Word
|
||||
sw t9, 0xC(sp) # Store Word
|
||||
sw t8, 0x10(sp) # Store Word
|
||||
sw s7, 0x14(sp) # Store Word
|
||||
sw s6, 0x18(sp) # Store Word
|
||||
sw s5, 0x1C(sp) # Store Word
|
||||
sw s4, 0x20(sp) # Store Word
|
||||
sw s3, 0x24(sp) # Store Word
|
||||
sw s2, 0x28(sp) # Store Word
|
||||
sw s1, 0x2C(sp) # Store Word
|
||||
sw s0, 0x30(sp) # Store Word
|
||||
sw t7, 0x34(sp) # Store Word
|
||||
sw t6, 0x38(sp) # Store Word
|
||||
sw t5, 0x3C(sp) # Store Word
|
||||
sw t4, 0x40(sp) # Store Word
|
||||
sw t3, 0x44(sp) # Store Word
|
||||
sw t2, 0x48(sp) # Store Word
|
||||
sw t1, 0x4C(sp) # Store Word
|
||||
sw t0, 0x50(sp) # Store Word
|
||||
sw a3, 0x54(sp) # Store Word
|
||||
sw a2, 0x58(sp) # Store Word
|
||||
sw a1, 0x5C(sp) # Store Word
|
||||
sw a0, 0x60(sp) # Store Word
|
||||
sw v1, 0x64(sp) # Store Word
|
||||
sw v0, 0x68(sp) # Store Word
|
||||
sw $1, 0x6C(sp) # Store Word
|
||||
mflo t0 # Move F LO
|
||||
nop
|
||||
sw t0, 0x70(sp) # Store Word
|
||||
mfhi t0 # Move F HI
|
||||
nop
|
||||
sw t0, 0x74(sp) # Store Word
|
||||
mfc0 t0, C0_STATUS # Status register
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sw t0, 0x78(sp) # Store Word
|
||||
mfc0 t0, C0_EPC # Exception Program Counter
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sw t0, 0x7C(sp) # Store Word
|
||||
li k1, 0x7C # Load Immediate
|
||||
mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
|
||||
and k0, k1 # AND
|
||||
beq zero, k0, _int # Branch on Equal
|
||||
nop
|
||||
la k0, _exception
|
||||
jr k0
|
||||
nop
|
||||
|
||||
.global _int
|
||||
.type _int,@function
|
||||
_int:
|
||||
jal intr_handler # Jump And Link
|
||||
nop
|
||||
lw ra, 0(sp) # Load Word
|
||||
lw fp, 4(sp) # Load Word
|
||||
sw gp, 8(sp) # Store Word
|
||||
lw t9, 0xC(sp) # Load Word
|
||||
lw t8, 0x10(sp) # Load Word
|
||||
lw s7, 0x14(sp) # Load Word
|
||||
lw s6, 0x18(sp) # Load Word
|
||||
lw s5, 0x1C(sp) # Load Word
|
||||
lw s4, 0x20(sp) # Load Word
|
||||
lw s3, 0x24(sp) # Load Word
|
||||
lw s2, 0x28(sp) # Load Word
|
||||
lw s1, 0x2C(sp) # Load Word
|
||||
lw s0, 0x30(sp) # Load Word
|
||||
lw t7, 0x34(sp) # Load Word
|
||||
lw t6, 0x38(sp) # Load Word
|
||||
lw t5, 0x3C(sp) # Load Word
|
||||
lw t4, 0x40(sp) # Load Word
|
||||
lw t3, 0x44(sp) # Load Word
|
||||
lw t2, 0x48(sp) # Load Word
|
||||
lw t1, 0x4C(sp) # Load Word
|
||||
lw t0, 0x50(sp) # Load Word
|
||||
lw a3, 0x54(sp) # Load Word
|
||||
lw a2, 0x58(sp) # Load Word
|
||||
lw a1, 0x5C(sp) # Load Word
|
||||
lw a0, 0x60(sp) # Load Word
|
||||
lw v1, 0x64(sp) # Load Word
|
||||
lw v0, 0x68(sp) # Load Word
|
||||
lw v1, 0x6C(sp) # Load Word
|
||||
lw k0, 0x70(sp) # Load Word
|
||||
mtlo k0 # Move To LO
|
||||
nop
|
||||
lw k0, 0x74(sp) # Load Word
|
||||
mthi k0 # Move To HI
|
||||
nop
|
||||
lw k0, 0x78(sp) # Load Word
|
||||
nop
|
||||
mtc0 k0, C0_STATUS # Status register
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
lw k0, 0x7C(sp) # Load Word
|
||||
nop
|
||||
mtc0 k0, C0_EPC # Exception Program Counter
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
sll zero, 1 # Shift Left Logical
|
||||
addiu sp, 0x80 # Add Immediate Unsigned
|
||||
eret # Exception Return
|
||||
nop
|
||||
|
||||
.extern _except_handler
|
||||
.global _exception
|
||||
.type _exception,@function
|
||||
_exception:
|
||||
move a0, sp
|
||||
mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
|
||||
mfc0 a2, C0_EPC # Exception Program Counter
|
||||
la k0, except_handler # Load Address
|
||||
jr k0 # Jump Register
|
||||
nop
|
||||
|
||||
.set reorder
|
||||
94
firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
Executable file
94
firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
Executable file
|
|
@ -0,0 +1,94 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "lcd.h"
|
||||
#include "lcd-target.h"
|
||||
|
||||
static volatile bool _lcd_on = false;
|
||||
static volatile bool lcd_poweroff = false;
|
||||
|
||||
/* LCD init */
|
||||
void lcd_init_device(void)
|
||||
{
|
||||
lcd_init_controller();
|
||||
_lcd_on = true;
|
||||
}
|
||||
|
||||
void lcd_enable(bool state)
|
||||
{
|
||||
if(state)
|
||||
lcd_on();
|
||||
else
|
||||
lcd_off();
|
||||
|
||||
_lcd_on = state;
|
||||
}
|
||||
|
||||
bool lcd_enabled(void)
|
||||
{
|
||||
return _lcd_on;
|
||||
}
|
||||
|
||||
#define LCDADDR(x, y) ((unsigned int)&lcd_framebuffer[(y)][(x)])
|
||||
#define LCD_UNCACHED(addr) ((unsigned int)(addr) | 0xA0000000)
|
||||
|
||||
/* Update a fraction of the display. */
|
||||
void lcd_update_rect(int x, int y, int width, int height)
|
||||
{
|
||||
/* HACKY... */
|
||||
x=0; y=0; width=400; height=240;
|
||||
lcd_set_target(x, y, width-1, height-1);
|
||||
|
||||
REG_DMAC_DCCSR(0) = 0;
|
||||
REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
|
||||
REG_DMAC_DSAR(0) = LCDADDR(x,y) & 0x1FFFFFFF;
|
||||
#if 0
|
||||
REG_DMAC_DTAR(0) = LCD_UNCACHED(SLCD_FIFO);
|
||||
#else
|
||||
REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */
|
||||
#endif
|
||||
REG_DMAC_DTCR(0) = (width*height);
|
||||
|
||||
REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
|
||||
| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
|
||||
REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
|
||||
|
||||
jz_flush_icache();
|
||||
|
||||
REG_DMAC_DMACR = DMAC_DMACR_DMAE;
|
||||
|
||||
while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
|
||||
asm("nop");
|
||||
|
||||
//REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_TT;
|
||||
}
|
||||
|
||||
/* Update the display.
|
||||
This must be called after all other LCD functions that change the display. */
|
||||
void lcd_update(void)
|
||||
{
|
||||
if (!_lcd_on)
|
||||
return;
|
||||
|
||||
lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
|
||||
}
|
||||
28
firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h
Executable file
28
firmware/target/mips/ingenic_jz47xx/onda_vx747/adc-target.h
Executable file
|
|
@ -0,0 +1,28 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef _ADC_TARGET_H_
|
||||
#define _ADC_TARGET_H_
|
||||
|
||||
#define NUM_ADC_CHANNELS 4
|
||||
|
||||
#define ADC_BUTTONS 0
|
||||
|
||||
#endif /* _ADC_TARGET_H_ */
|
||||
80
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
Executable file
80
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
Executable file
|
|
@ -0,0 +1,80 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "backlight-target.h"
|
||||
|
||||
#define GPIO_PWM 123
|
||||
#define PWM_CHN 7
|
||||
#define PWM_FULL 101
|
||||
|
||||
static void set_backlight(int unk, int val)
|
||||
{
|
||||
if(val == 0)
|
||||
__gpio_as_pwm7();
|
||||
else
|
||||
{
|
||||
REG_TCU_TCSR(7) |= 2;
|
||||
REG_TCU_TCSR(7) &= ~0x100;
|
||||
int tmp;
|
||||
tmp = (unk/2 + __cpm_get_rtcclk()) / unk;
|
||||
if(tmp > 0xFFFF)
|
||||
tmp = 0xFFFF;
|
||||
|
||||
__tcu_set_half_data(7, (tmp * unk * 1374389535) >> 5);
|
||||
__tcu_set_full_data(7, tmp);
|
||||
|
||||
REG_TCU_TSCR = (1 << 7);
|
||||
REG_TCU_TESR = (1 << 7);
|
||||
|
||||
__tcu_enable_pwm_output(7);
|
||||
}
|
||||
__tcu_set_count(7, 0);
|
||||
}
|
||||
|
||||
bool _backlight_init(void)
|
||||
{
|
||||
__gpio_as_pwm7();
|
||||
|
||||
__tcu_stop_counter(7);
|
||||
__tcu_disable_pwm_output(7);
|
||||
|
||||
set_backlight(300, 7);
|
||||
|
||||
return true;
|
||||
}
|
||||
void _backlight_on(void)
|
||||
{
|
||||
set_backlight(300, 7);
|
||||
}
|
||||
void _backlight_off(void)
|
||||
{
|
||||
set_backlight(300, 0);
|
||||
}
|
||||
|
||||
#ifdef HAVE_BACKLIGHT_BRIGHTNESS
|
||||
void _backlight_set_brightness(int brightness)
|
||||
{
|
||||
(void)brightness;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
37
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h
Executable file
37
firmware/target/mips/ingenic_jz47xx/onda_vx747/backlight-target.h
Executable file
|
|
@ -0,0 +1,37 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef BACKLIGHT_TARGET_H
|
||||
#define BACKLIGHT_TARGET_H
|
||||
|
||||
#ifdef BOOTLOADER
|
||||
#define BACKLIGHT_DRIVER_CLOSE
|
||||
/* Force the whole driver to be built */
|
||||
#define BACKLIGHT_FULL_INIT
|
||||
#endif
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
bool _backlight_init(void);
|
||||
void _backlight_on(void);
|
||||
void _backlight_off(void);
|
||||
void _backlight_set_brightness(int brightness);
|
||||
|
||||
#endif /* BACKLIGHT_TARGET_H */
|
||||
123
firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
Executable file
123
firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c
Executable file
|
|
@ -0,0 +1,123 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "button-target.h"
|
||||
|
||||
#define BTN_VOL_DOWN (1 << 27)
|
||||
#define BTN_VOL_UP (1 << 0)
|
||||
#define BTN_MENU (1 << 1)
|
||||
#define BTN_OFF (1 << 29)
|
||||
#define BTN_HOLD (1 << 16)
|
||||
#define BTN_MASK (BTN_VOL_DOWN | BTN_VOL_UP \
|
||||
| BTN_MENU | BTN_OFF )
|
||||
|
||||
#define SADC_CFG_INIT ( \
|
||||
(2 << SADC_CFG_CLKOUT_NUM_BIT) | \
|
||||
SADC_CFG_XYZ1Z2 | \
|
||||
SADC_CFG_SNUM_5 | \
|
||||
(1 << SADC_CFG_CLKDIV_BIT) | \
|
||||
SADC_CFG_PBAT_HIGH | \
|
||||
SADC_CFG_CMD_INT_PEN )
|
||||
|
||||
bool button_hold(void)
|
||||
{
|
||||
return (REG_GPIO_PXPIN(3) ^ BTN_HOLD ? 1 : 0);
|
||||
}
|
||||
|
||||
void button_init_device(void)
|
||||
{
|
||||
REG_SADC_ENA = 0;
|
||||
REG_SADC_STATE &= (~REG_SADC_STATE);
|
||||
REG_SADC_CTRL = 0x1f;
|
||||
|
||||
__cpm_start_sadc();
|
||||
REG_SADC_CFG = SADC_CFG_INIT;
|
||||
|
||||
REG_SADC_SAMETIME = 1;
|
||||
REG_SADC_WAITTIME = 1000; //per 100 HZ
|
||||
REG_SADC_STATE &= (~REG_SADC_STATE);
|
||||
REG_SADC_CTRL &= (~(SADC_CTRL_PENDM | SADC_CTRL_TSRDYM));
|
||||
REG_SADC_ENA = SADC_ENA_TSEN; // | REG_SADC_ENA;//SADC_ENA_TSEN | SADC_ENA_PBATEN | SADC_ENA_SADCINEN;
|
||||
}
|
||||
|
||||
static int touch_to_pixels(short x, short y)
|
||||
{
|
||||
/* X:300 -> 3800 Y:300->3900 */
|
||||
x -= 300;
|
||||
y -= 300;
|
||||
|
||||
x /= 3200 / LCD_WIDTH;
|
||||
y /= 3600 / LCD_HEIGHT;
|
||||
|
||||
return (x << 16) | y;
|
||||
}
|
||||
|
||||
int button_read_device(int *data)
|
||||
{
|
||||
unsigned int key = ~REG_GPIO_PXPIN(3);
|
||||
int ret = 0;
|
||||
if(key & BTN_MASK)
|
||||
{
|
||||
if(key & BTN_VOL_DOWN)
|
||||
ret |= BUTTON_VOL_DOWN;
|
||||
if(key & BTN_VOL_UP)
|
||||
ret |= BUTTON_VOL_UP;
|
||||
if(key & BTN_MENU)
|
||||
ret |= BUTTON_MENU;
|
||||
if(key & BTN_OFF)
|
||||
ret |= BUTTON_POWER;
|
||||
}
|
||||
|
||||
if(REG_SADC_STATE & (SADC_CTRL_TSRDYM|SADC_STATE_PEND))
|
||||
{
|
||||
if(REG_SADC_STATE & SADC_CTRL_PENDM)
|
||||
{
|
||||
REG_SADC_CTRL &= (~(SADC_CTRL_PENUM | SADC_CTRL_TSRDYM));
|
||||
REG_SADC_CTRL |= (SADC_CTRL_PENDM);
|
||||
unsigned int dat;
|
||||
unsigned short xData,yData;
|
||||
short tsz1Data,tsz2Data;
|
||||
|
||||
dat = REG_SADC_TSDAT;
|
||||
|
||||
xData = (dat >> 0) & 0xfff;
|
||||
yData = (dat >> 16) & 0xfff;
|
||||
|
||||
dat = REG_SADC_TSDAT;
|
||||
tsz1Data = (dat >> 0) & 0xfff;
|
||||
tsz2Data = (dat >> 16) & 0xfff;
|
||||
|
||||
*data = touch_to_pixels(xData, yData);
|
||||
|
||||
tsz1Data = tsz2Data - tsz1Data;
|
||||
}
|
||||
REG_SADC_STATE = 0;
|
||||
//__intc_unmask_irq(IRQ_SADC);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
void button_set_touch_available(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
69
firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h
Executable file
69
firmware/target/mips/ingenic_jz47xx/onda_vx747/button-target.h
Executable file
|
|
@ -0,0 +1,69 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef BUTTON_TARGET_H
|
||||
#define BUTTON_TARGET_H
|
||||
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "config.h"
|
||||
|
||||
#define HAS_BUTTON_HOLD
|
||||
|
||||
bool button_hold(void);
|
||||
void button_init_device(void);
|
||||
int button_read_device(int *data);
|
||||
void button_set_touch_available(void);
|
||||
|
||||
/* Main unit's buttons */
|
||||
#define BUTTON_POWER 0x00000001
|
||||
#define BUTTON_VOL_UP 0x00000002
|
||||
#define BUTTON_VOL_DOWN 0x00000004
|
||||
#define BUTTON_MENU 0x00000008
|
||||
|
||||
/* Compatibility hacks for flipping. Needs a somewhat better fix. */
|
||||
#define BUTTON_LEFT BUTTON_MIDLEFT
|
||||
#define BUTTON_RIGHT BUTTON_MIDRIGHT
|
||||
#define BUTTON_UP BUTTON_TOPMIDDLE
|
||||
#define BUTTON_DOWN BUTTON_BOTTOMMIDDLE
|
||||
|
||||
/* Touchpad Screen Area Buttons */
|
||||
#define BUTTON_TOPLEFT 0x00000010
|
||||
#define BUTTON_TOPMIDDLE 0x00000020
|
||||
#define BUTTON_TOPRIGHT 0x00000040
|
||||
#define BUTTON_MIDLEFT 0x00000080
|
||||
#define BUTTON_CENTER 0x00000100
|
||||
#define BUTTON_MIDRIGHT 0x00000200
|
||||
#define BUTTON_BOTTOMLEFT 0x00000400
|
||||
#define BUTTON_BOTTOMMIDDLE 0x00000800
|
||||
#define BUTTON_BOTTOMRIGHT 0x00001000
|
||||
|
||||
#define BUTTON_TOUCH 0x00002000
|
||||
|
||||
#define BUTTON_MAIN 0x3FFF
|
||||
|
||||
/* No remote */
|
||||
#define BUTTON_REMOTE 0
|
||||
|
||||
/* Software power-off */
|
||||
#define POWEROFF_BUTTON BUTTON_POWER
|
||||
#define POWEROFF_COUNT 10
|
||||
|
||||
#endif /* BUTTON_TARGET_H */
|
||||
201
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
Executable file
201
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
Executable file
|
|
@ -0,0 +1,201 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "lcd-target.h"
|
||||
|
||||
#define PIN_CS_N (32*1+17) /* Chip select */
|
||||
#define PIN_RESET_N (32*1+18) /* Reset */
|
||||
|
||||
#define my__gpio_as_lcd_16bit() \
|
||||
do { \
|
||||
REG_GPIO_PXFUNS(2) = 0x001cffff; \
|
||||
REG_GPIO_PXSELC(2) = 0x001cffff; \
|
||||
REG_GPIO_PXPES(2) = 0x001cffff; \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define SLEEP(x) for(i=0; i<x; i++) asm("nop"); asm("nop");
|
||||
#define DELAY SLEEP(700000);
|
||||
static void _display_pin_init(void)
|
||||
{
|
||||
int i;
|
||||
my__gpio_as_lcd_16bit();
|
||||
__gpio_as_output(PIN_CS_N);
|
||||
__gpio_as_output(PIN_RESET_N);
|
||||
__gpio_clear_pin(PIN_CS_N);
|
||||
|
||||
__gpio_set_pin(PIN_RESET_N);
|
||||
DELAY;
|
||||
__gpio_clear_pin(PIN_RESET_N);
|
||||
DELAY;
|
||||
__gpio_set_pin(PIN_RESET_N);
|
||||
DELAY;
|
||||
}
|
||||
|
||||
#define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY);
|
||||
#define SLCD_SET_DATA(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_DATA;
|
||||
#define SLCD_SET_COMMAND(x) WAIT_ON_SLCD; REG_SLCD_DATA = (x) | SLCD_DATA_RS_COMMAND;
|
||||
#define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val);
|
||||
static void _display_on(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
SLCD_SEND_COMMAND(0x600, 1);
|
||||
SLEEP(700000);
|
||||
SLCD_SEND_COMMAND(0x600, 0);
|
||||
SLEEP(700000);
|
||||
SLCD_SEND_COMMAND(0x606, 0);
|
||||
|
||||
SLCD_SEND_COMMAND(1, 0x100);
|
||||
SLCD_SEND_COMMAND(2, 0x100);
|
||||
SLCD_SEND_COMMAND(3, 0x1028);
|
||||
SLCD_SEND_COMMAND(8, 0x503);
|
||||
SLCD_SEND_COMMAND(9, 1);
|
||||
SLCD_SEND_COMMAND(0xB, 0x10);
|
||||
SLCD_SEND_COMMAND(0xC, 0);
|
||||
SLCD_SEND_COMMAND(0xF, 0);
|
||||
SLCD_SEND_COMMAND(7, 1);
|
||||
SLCD_SEND_COMMAND(0x10, 0x12);
|
||||
SLCD_SEND_COMMAND(0x11, 0x202);
|
||||
SLCD_SEND_COMMAND(0x12, 0x300);
|
||||
SLCD_SEND_COMMAND(0x20, 0x21e);
|
||||
SLCD_SEND_COMMAND(0x21, 0x202);
|
||||
SLCD_SEND_COMMAND(0x22, 0x100);
|
||||
SLCD_SEND_COMMAND(0x90, 0x8000);
|
||||
SLCD_SEND_COMMAND(0x100, 0x16b0);
|
||||
SLCD_SEND_COMMAND(0x101, 0x147);
|
||||
SLCD_SEND_COMMAND(0x102, 0x1bd);
|
||||
SLCD_SEND_COMMAND(0x103, 0x2f00);
|
||||
SLCD_SEND_COMMAND(0x107, 0);
|
||||
SLCD_SEND_COMMAND(0x110, 1);
|
||||
SLCD_SEND_COMMAND(0x200, 0); /* set cursor at x_start */
|
||||
SLCD_SEND_COMMAND(0x201, 0); /* set cursor at y_start */
|
||||
SLCD_SEND_COMMAND(0x210, 0); /* y_start*/
|
||||
SLCD_SEND_COMMAND(0x211, 239); /* y_end */
|
||||
SLCD_SEND_COMMAND(0x212, 0); /* x_start */
|
||||
SLCD_SEND_COMMAND(0x213, 399); /* x_end */
|
||||
SLCD_SEND_COMMAND(0x280, 0);
|
||||
SLCD_SEND_COMMAND(0x281, 6);
|
||||
SLCD_SEND_COMMAND(0x282, 0);
|
||||
SLCD_SEND_COMMAND(0x300, 0x101);
|
||||
SLCD_SEND_COMMAND(0x301, 0xb27);
|
||||
SLCD_SEND_COMMAND(0x302, 0x132a);
|
||||
SLCD_SEND_COMMAND(0x303, 0x2a13);
|
||||
SLCD_SEND_COMMAND(0x304, 0x270b);
|
||||
SLCD_SEND_COMMAND(0x305, 0x101);
|
||||
SLCD_SEND_COMMAND(0x306, 0x1205);
|
||||
SLCD_SEND_COMMAND(0x307, 0x512);
|
||||
SLCD_SEND_COMMAND(0x308, 5);
|
||||
SLCD_SEND_COMMAND(0x309, 3);
|
||||
SLCD_SEND_COMMAND(0x30a, 0xf04);
|
||||
SLCD_SEND_COMMAND(0x30b, 0xf00);
|
||||
SLCD_SEND_COMMAND(0x30c, 0xf);
|
||||
SLCD_SEND_COMMAND(0x30d, 0x40f);
|
||||
SLCD_SEND_COMMAND(0x30e, 0x300);
|
||||
SLCD_SEND_COMMAND(0x30f, 0x500);
|
||||
SLCD_SEND_COMMAND(0x400, 0x3100);
|
||||
SLCD_SEND_COMMAND(0x401, 1);
|
||||
SLCD_SEND_COMMAND(0x404, 0);
|
||||
SLCD_SEND_COMMAND(0x500, 0);
|
||||
SLCD_SEND_COMMAND(0x501, 0);
|
||||
SLCD_SEND_COMMAND(0x502, 0);
|
||||
SLCD_SEND_COMMAND(0x503, 0);
|
||||
SLCD_SEND_COMMAND(0x504, 0);
|
||||
SLCD_SEND_COMMAND(0x505, 0);
|
||||
SLCD_SEND_COMMAND(0x606, 0);
|
||||
SLCD_SEND_COMMAND(0x6f0, 0);
|
||||
SLCD_SEND_COMMAND(0x7f0, 0x5420);
|
||||
SLCD_SEND_COMMAND(0x7f3, 0x288a);
|
||||
SLCD_SEND_COMMAND(0x7f4, 0x22);
|
||||
SLCD_SEND_COMMAND(0x7f5, 1);
|
||||
SLCD_SEND_COMMAND(0x7f0, 0);
|
||||
|
||||
SLCD_SEND_COMMAND(7, 0x173);
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(7, 0x171);
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(7, 0x173);
|
||||
SLEEP(3500000);
|
||||
}
|
||||
|
||||
static void _set_lcd_bus(void)
|
||||
{
|
||||
REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
|
||||
REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;
|
||||
|
||||
REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT
|
||||
| SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
|
||||
| SLCD_CFG_TYPE_PARALLEL);
|
||||
|
||||
REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
|
||||
}
|
||||
|
||||
static void _set_lcd_clock(void)
|
||||
{
|
||||
unsigned int val;
|
||||
int pll_div;
|
||||
|
||||
__cpm_stop_lcd();
|
||||
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
|
||||
pll_div = pll_div ? 1 : 2 ;
|
||||
val = ( __cpm_get_pllout()/pll_div ) / 336000000;
|
||||
val--;
|
||||
if ( val > 0x1ff )
|
||||
{
|
||||
//printf("CPM_LPCDR too large, set it to 0x1ff\n");
|
||||
val = 0x1ff;
|
||||
}
|
||||
__cpm_set_pixdiv(val);
|
||||
__cpm_start_lcd();
|
||||
}
|
||||
|
||||
void lcd_init_controller(void)
|
||||
{
|
||||
int i;
|
||||
_display_pin_init();
|
||||
_set_lcd_bus();
|
||||
_set_lcd_clock();
|
||||
SLEEP(1000);
|
||||
_display_on();
|
||||
}
|
||||
|
||||
void lcd_set_target(short x, short y, short width, short height)
|
||||
{
|
||||
SLCD_SEND_COMMAND(0x210, y); /* y_start */
|
||||
SLCD_SEND_COMMAND(0x211, y+height); /* y_end */
|
||||
SLCD_SEND_COMMAND(0x212, x); /* x_start */
|
||||
SLCD_SEND_COMMAND(0x213, x+width); /* x_end */
|
||||
SLCD_SEND_COMMAND(0x200, x); /* set cursor at x_start */
|
||||
SLCD_SEND_COMMAND(0x201, y); /* set cursor at y_start */
|
||||
SLCD_SET_COMMAND(0x202); /* write data? */
|
||||
}
|
||||
|
||||
void lcd_on(void)
|
||||
{
|
||||
_display_on();
|
||||
}
|
||||
|
||||
void lcd_off(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
36
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h
Executable file
36
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-target.h
Executable file
|
|
@ -0,0 +1,36 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef LCD_TARGET_H
|
||||
#define LCD_TARGET_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
void lcd_enable(bool state);
|
||||
bool lcd_enabled(void);
|
||||
void lcd_init_device(void);
|
||||
|
||||
|
||||
void lcd_init_controller(void);
|
||||
void lcd_set_target(short x, short y, short width, short height);
|
||||
void lcd_on(void);
|
||||
void lcd_off(void);
|
||||
|
||||
#endif /* LCD_TARGET_H */
|
||||
26
firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
Executable file
26
firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
Executable file
|
|
@ -0,0 +1,26 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef USB_TARGET_H
|
||||
#define USB_TARGET_H
|
||||
|
||||
void usb_init_device(void);
|
||||
|
||||
#endif
|
||||
71
firmware/target/mips/ingenic_jz47xx/system-jz4740.c
Executable file
71
firmware/target/mips/ingenic_jz47xx/system-jz4740.c
Executable file
|
|
@ -0,0 +1,71 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "mipsregs.h"
|
||||
|
||||
void intr_handler(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void except_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
|
||||
{
|
||||
(void)stack_ptr;
|
||||
(void)cause;
|
||||
(void)epc;
|
||||
REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
|
||||
while(1);
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void cli(void)
|
||||
{
|
||||
register unsigned int t;
|
||||
t = read_c0_status();
|
||||
t &= ~1;
|
||||
write_c0_status(t);
|
||||
}
|
||||
|
||||
unsigned int mips_get_sr(void)
|
||||
{
|
||||
unsigned int t = read_c0_status();
|
||||
return t;
|
||||
}
|
||||
|
||||
void sti(void)
|
||||
{
|
||||
register unsigned int t;
|
||||
t = read_c0_status();
|
||||
t |= 1;
|
||||
t &= ~2;
|
||||
write_c0_status(t);
|
||||
}
|
||||
|
||||
void tick_start(unsigned int interval_in_ms)
|
||||
{
|
||||
(void)interval_in_ms;
|
||||
}
|
||||
103
firmware/target/mips/ingenic_jz47xx/system-target.h
Executable file
103
firmware/target/mips/ingenic_jz47xx/system-target.h
Executable file
|
|
@ -0,0 +1,103 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "mipsregs.h"
|
||||
|
||||
/* Core-level interrupt masking */
|
||||
|
||||
/* This one returns the old status */
|
||||
#define HIGHEST_IRQ_LEVEL 0
|
||||
|
||||
#define set_irq_level(status) \
|
||||
set_interrupt_status((status), ST0_IE)
|
||||
#define set_fiq_status(status) \
|
||||
set_interrupt_status((status), ST0_IE)
|
||||
|
||||
static inline int set_interrupt_status(int status, int mask)
|
||||
{
|
||||
unsigned int res, oldstatus;
|
||||
|
||||
res = oldstatus = read_c0_status();
|
||||
res &= ~mask;
|
||||
res |= (status & mask);
|
||||
write_c0_status(res);
|
||||
|
||||
return oldstatus;
|
||||
}
|
||||
|
||||
static inline void enable_interrupt(void)
|
||||
{
|
||||
/* Set IE bit */
|
||||
set_c0_status(ST0_IE);
|
||||
}
|
||||
|
||||
static inline void disable_interrupt(void)
|
||||
{
|
||||
/* Clear IE bit */
|
||||
clear_c0_status(ST0_IE);
|
||||
}
|
||||
|
||||
#define disable_irq() \
|
||||
disable_interrupt()
|
||||
|
||||
#define enable_irq() \
|
||||
enable_interrupt()
|
||||
|
||||
#define disable_fiq() \
|
||||
disable_interrupt()
|
||||
|
||||
#define enable_fiq() \
|
||||
enable_interrupt()
|
||||
|
||||
static inline int disable_interrupt_save(int mask)
|
||||
{
|
||||
unsigned int oldstatus;
|
||||
|
||||
oldstatus = read_c0_status();
|
||||
write_c0_status(oldstatus | mask);
|
||||
|
||||
return oldstatus;
|
||||
}
|
||||
|
||||
#define disable_irq_save() \
|
||||
disable_interrupt_save(ST0_IE)
|
||||
|
||||
#define disable_fiq_save() \
|
||||
disable_interrupt_save(ST0_IE)
|
||||
|
||||
static inline void restore_interrupt(int status)
|
||||
{
|
||||
write_c0_status(status);
|
||||
}
|
||||
|
||||
#define restore_irq(cpsr) \
|
||||
restore_interrupt(cpsr)
|
||||
|
||||
#define restore_fiq(cpsr) \
|
||||
restore_interrupt(cpsr)
|
||||
|
||||
#define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff)
|
||||
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
|
||||
|
||||
void sti(void);
|
||||
void cli(void);
|
||||
|
|
@ -985,6 +985,149 @@ static inline void core_sleep(void)
|
|||
: : "z"(&SBYCR-GBR) : "r1");
|
||||
}
|
||||
|
||||
#elif CPU_MIPS == 32
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Start the thread running and terminate it if it returns
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
void start_thread(void); /* Provide C access to ASM label */
|
||||
#if 0
|
||||
static void __attribute__((used)) __start_thread(void)
|
||||
{
|
||||
|
||||
/* $v0 = context */
|
||||
asm volatile (
|
||||
".set noreorder \n"
|
||||
"_start_thread: \n" /* Start here - no naked attribute */
|
||||
"lw $8, (4)$2 \n" /* Fetch thread function pointer ($8 = $t0, $2 = $v0) */
|
||||
"lw $29, (108)$2 \n" /* Set initial sp(=$29) */
|
||||
"jalr $8 \n" /* Start the thread ($8 = $t0,)*/
|
||||
"sw $0, (116)$2 \n" /* Clear start address ($2 = $v0) */
|
||||
".set reorder \n"
|
||||
);
|
||||
thread_exit();
|
||||
|
||||
}
|
||||
#else
|
||||
void start_thread(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Place context pointer in $v0 slot, function pointer in $v1 slot, and
|
||||
* start_thread pointer in context_start */
|
||||
#define THREAD_STARTUP_INIT(core, thread, function) \
|
||||
({ (thread)->context.r[0] = (uint32_t)&(thread)->context, \
|
||||
(thread)->context.r[1] = (uint32_t)(function), \
|
||||
(thread)->context.start = (uint32_t)start_thread; })
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Store non-volatile context.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void store_context(void* addr)
|
||||
{
|
||||
#if 0
|
||||
asm volatile (
|
||||
".set noreorder \n"
|
||||
".set noat \n"
|
||||
"sw $1, (0)%0 \n"
|
||||
"sw $2,(4)%0 \n" /* $v0 */
|
||||
"sw $3,(8)%0 \n" /* $v1 */
|
||||
"sw $4,(12)%0 \n" /* $a0 */
|
||||
"sw $5,(16)%0 \n" /* $a1 */
|
||||
"sw $6,(20)%0 \n" /* $a2 */
|
||||
"sw $7,(24)%0 \n" /* $a3 */
|
||||
"sw $8,(28)%0 \n" /* $t0 */
|
||||
"sw $9,(32)%0 \n" /* $t1 */
|
||||
"sw $10,(36)%0 \n" /* $t2 */
|
||||
"sw $11,(40)%0 \n" /* $t3 */
|
||||
"sw $12,(44)%0 \n" /* $t4 */
|
||||
"sw $13,(48)%0 \n" /* $t5 */
|
||||
"sw $14,(52)%0 \n" /* $t6 */
|
||||
"sw $15,(56)%0 \n" /* $t7 */
|
||||
"sw $24,(60)%0 \n" /* $t8 */
|
||||
"sw $25,(64)%0 \n" /* $t9 */
|
||||
"sw $16,(68)%0 \n" /* $s0 */
|
||||
"sw $17,(72)%0 \n" /* $s1 */
|
||||
"sw $18,(76)%0 \n" /* $s2 */
|
||||
"sw $19,(80)%0 \n" /* $s3 */
|
||||
"sw $20,(84)%0 \n" /* $s4 */
|
||||
"sw $21,(88)%0 \n" /* $s5 */
|
||||
"sw $22,(92)%0 \n" /* $s6 */
|
||||
"sw $23,(96)%0 \n" /* $s7 */
|
||||
"sw $28,(100)%0 \n" /* gp */
|
||||
"sw $30,(104)%0 \n" /* fp */
|
||||
"sw $29,(108)%0 \n" /* sp */
|
||||
"sw $31,(112)%0 \n" /* ra */
|
||||
".set reorder \n"
|
||||
: : "r" (addr)
|
||||
);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Load non-volatile context.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void load_context(const void* addr)
|
||||
{
|
||||
#if 0
|
||||
asm volatile (
|
||||
".set noat \n"
|
||||
".set noreorder \n"
|
||||
"lw $8, 116(%0) \n" /* Get start address ($8 = $t0) */
|
||||
//"tst r0, r0 \n"
|
||||
"j .running \n" /* NULL -> already running */
|
||||
"jr $8 \n" /* $t0 = $8 = context */
|
||||
".running: \n"
|
||||
"lw $1, (0)%0 \n"
|
||||
"lw $2,(4)%0 \n" /* $v0 */
|
||||
"lw $3,(8)%0 \n" /* $v1 */
|
||||
"lw $4,(12)%0 \n" /* $a0 */
|
||||
"lw $5,(16)%0 \n" /* $a1 */
|
||||
"lw $6,(20)%0 \n" /* $a2 */
|
||||
"lw $7,(24)%0 \n" /* $a3 */
|
||||
"lw $8,(28)%0 \n" /* $t0 */
|
||||
"lw $9,(32)%0 \n" /* $t1 */
|
||||
"lw $10,(36)%0 \n" /* $t2 */
|
||||
"lw $11,(40)%0 \n" /* $t3 */
|
||||
"lw $12,(44)%0 \n" /* $t4 */
|
||||
"lw $13,(48)%0 \n" /* $t5 */
|
||||
"lw $14,(52)%0 \n" /* $t6 */
|
||||
"lw $15,(56)%0 \n" /* $t7 */
|
||||
"lw $24,(60)%0 \n" /* $t8 */
|
||||
"lw $25,(64)%0 \n" /* $t9 */
|
||||
"lw $16,(68)%0 \n" /* $s0 */
|
||||
"lw $17,(72)%0 \n" /* $s1 */
|
||||
"lw $18,(76)%0 \n" /* $s2 */
|
||||
"lw $19,(80)%0 \n" /* $s3 */
|
||||
"lw $20,(84)%0 \n" /* $s4 */
|
||||
"lw $21,(88)%0 \n" /* $s5 */
|
||||
"lw $22,(92)%0 \n" /* $s6 */
|
||||
"lw $23,(96)%0 \n" /* $s7 */
|
||||
"lw $28,(100)%0 \n" /* gp */
|
||||
"lw $30,(104)%0 \n" /* fp */
|
||||
"lw $29,(108)%0 \n" /* sp */
|
||||
"lw $31,(112)%0 \n" /* ra */
|
||||
".set reorder \n"
|
||||
: : "r" (addr) : "v0" /* only! */
|
||||
);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
* Put core in a power-saving state.
|
||||
*---------------------------------------------------------------------------
|
||||
*/
|
||||
static inline void core_sleep(void)
|
||||
{
|
||||
asm volatile("nop\n");
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_CPU == */
|
||||
|
||||
/*
|
||||
|
|
@ -1909,6 +2052,8 @@ static inline void block_thread_on_l(struct thread_entry *thread,
|
|||
*/
|
||||
void switch_thread(void)
|
||||
{
|
||||
#ifndef ONDA_VX747
|
||||
|
||||
const unsigned int core = CURRENT_CORE;
|
||||
struct thread_entry *block = cores[core].block_task;
|
||||
struct thread_entry *thread = cores[core].running;
|
||||
|
|
@ -2043,6 +2188,8 @@ void switch_thread(void)
|
|||
#ifdef RB_PROFILE
|
||||
profile_thread_started(thread - threads);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------
|
||||
|
|
|
|||
34
tools/configure
vendored
34
tools/configure
vendored
|
|
@ -280,6 +280,15 @@ arm1136jfscc () {
|
|||
gccchoice="4.0.3"
|
||||
}
|
||||
|
||||
mipselcc () {
|
||||
prefixtools mipsel-linux-
|
||||
GCCOPTS="$CCOPTS -mips32 -mno-abicalls"
|
||||
GCCOPTIMIZE="-fomit-frame-pointer"
|
||||
GCCOPTS="$GCCOPTS -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -msoft-float -G 0"
|
||||
endian="little"
|
||||
gccchoice="4.1.2"
|
||||
}
|
||||
|
||||
whichadvanced () {
|
||||
##################################################################
|
||||
# Prompt for specific developer options
|
||||
|
|
@ -688,6 +697,9 @@ cat <<EOF
|
|||
90) Zen Vision:M 30GB 100) GoGear SA9200 110) M6SL
|
||||
91) Zen Vision:M 60GB 101) GoGear HDD1630
|
||||
92) Zen Vision
|
||||
|
||||
==Onda==
|
||||
120) VX747
|
||||
EOF
|
||||
|
||||
buildfor=`input`;
|
||||
|
|
@ -1747,6 +1759,28 @@ fi
|
|||
t_manufacturer="s5l8700"
|
||||
t_model="meizu-m6sl"
|
||||
;;
|
||||
|
||||
120|ondavx747)
|
||||
target_id=44
|
||||
modelname="ondavx747"
|
||||
target="-DONDA_VX747"
|
||||
memory=16 #FIXME
|
||||
mipselcc
|
||||
tool="cp"
|
||||
bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
|
||||
bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
|
||||
output="rockbox.vx747"
|
||||
appextra="recorder:gui"
|
||||
plugins="no" #FIXME
|
||||
swcodec="yes"
|
||||
toolset=$genericbitmaptools
|
||||
boottool="cp"
|
||||
bootoutput="rockboot.vx747"
|
||||
# architecture, manufacturer and model for the target-tree build
|
||||
t_cpu="mips"
|
||||
t_manufacturer="ingenic_jz47xx"
|
||||
t_model="onda_vx747"
|
||||
;;
|
||||
*)
|
||||
echo "Please select a supported target platform!"
|
||||
exit
|
||||
|
|
|
|||
|
|
@ -168,6 +168,8 @@ case $1 in
|
|||
;;
|
||||
[Ii])
|
||||
target="mipsel-elf"
|
||||
gccver="4.1.2"
|
||||
binutils="2.17"
|
||||
;;
|
||||
*)
|
||||
echo "unsupported"
|
||||
|
|
|
|||
Loading…
Reference in a new issue