2004-03-18 22:06:36 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Jens Arnold
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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2004-10-26 05:40:24 +00:00
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#include "config.h"
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2004-03-18 22:06:36 +00:00
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2006-02-22 19:03:20 +00:00
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#ifdef CPU_ARM
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.section .icode,"ax",%progbits
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2006-02-22 19:34:42 +00:00
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#else
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2004-03-18 22:06:36 +00:00
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.section .icode,"ax",@progbits
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2006-02-22 19:03:20 +00:00
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#endif
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2004-03-18 22:06:36 +00:00
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.align 2
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2004-10-26 05:40:24 +00:00
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#if CONFIG_CPU == SH7034
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2004-03-18 22:06:36 +00:00
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.global _memset
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.type _memset,@function
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/* Fills a memory region with specified byte value
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* This version is optimized for speed
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*
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* arguments:
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* r4 - start address
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* r5 - data
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* r6 - length
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*
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* return value:
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* r0 - start address (like ANSI version)
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*
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* register usage:
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* r0 - temporary
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2005-06-21 13:25:18 +00:00
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* r1 - start address +11 for main loop
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2004-03-18 22:06:36 +00:00
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* r4 - start address
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2005-06-21 13:25:18 +00:00
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* r5 - data (spread to all 4 bytes when using long stores)
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2004-03-18 22:06:36 +00:00
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* r6 - current address (runs down from end to start)
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*
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* The instruction order below is devised in a way to utilize the pipelining
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* of the SH1 to the max. The routine fills memory from end to start in
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* order to utilize the auto-decrementing store instructions.
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*/
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_memset:
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2005-06-07 17:27:47 +00:00
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neg r4,r0
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and #3,r0 /* r0 = (4 - align_offset) % 4 */
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add #4,r0
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cmp/hs r0,r6 /* at least one aligned longword to fill? */
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2004-03-18 22:06:36 +00:00
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add r4,r6 /* r6 = end_address */
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2005-06-07 17:27:47 +00:00
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bf .no_longs /* no, jump directly to byte loop */
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2004-03-18 22:06:36 +00:00
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extu.b r5,r5 /* start: spread data to all 4 bytes */
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swap.b r5,r0
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or r0,r5 /* data now in 2 lower bytes of r5 */
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swap.w r5,r0
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or r0,r5 /* data now in all 4 bytes of r5 */
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2005-06-07 17:27:47 +00:00
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mov r6,r0
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2005-06-21 13:25:18 +00:00
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tst #3,r0 /* r0 already long aligned? */
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bt .end_b1 /* yes: skip loop */
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2004-03-18 22:06:36 +00:00
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/* leading byte loop: sets 0..3 bytes */
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.loop_b1:
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2005-06-21 13:25:18 +00:00
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mov.b r5,@-r0 /* store byte */
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tst #3,r0 /* r0 long aligned? */
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bf .loop_b1 /* runs r0 down until long aligned */
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mov r0,r6 /* r6 = last long bound */
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nop /* keep alignment */
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2004-03-18 22:06:36 +00:00
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2005-06-07 17:27:47 +00:00
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.end_b1:
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2005-06-21 13:25:18 +00:00
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mov r4,r1 /* r1 = start_address... */
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add #11,r1 /* ... + 11, combined for rounding and offset */
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xor r1,r0
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2005-06-07 17:27:47 +00:00
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tst #4,r0 /* bit 2 tells whether an even or odd number of */
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bf .loop_odd /* longwords to set */
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2004-03-18 22:06:36 +00:00
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/* main loop: set 2 longs per pass */
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2005-06-07 17:27:47 +00:00
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.loop_2l:
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2004-03-18 22:06:36 +00:00
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mov.l r5,@-r6 /* store first long */
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2005-06-07 17:27:47 +00:00
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.loop_odd:
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2005-06-21 13:25:18 +00:00
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cmp/hi r1,r6 /* runs r6 down to first long bound */
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2004-03-18 22:06:36 +00:00
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mov.l r5,@-r6 /* store second long */
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2005-06-07 17:27:47 +00:00
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bt .loop_2l
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2004-03-18 22:06:36 +00:00
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2005-06-07 17:27:47 +00:00
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.no_longs:
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cmp/hi r4,r6 /* any bytes left? */
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bf .end_b2 /* no: skip loop */
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2004-03-18 22:06:36 +00:00
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/* trailing byte loop */
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.loop_b2:
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mov.b r5,@-r6 /* store byte */
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cmp/hi r4,r6 /* runs r6 down to the start address */
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bt .loop_b2
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2005-06-07 17:27:47 +00:00
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.end_b2:
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2004-03-18 22:06:36 +00:00
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rts
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mov r4,r0 /* return start address */
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.end:
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.size _memset,.end-_memset
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2005-07-18 12:40:29 +00:00
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#elif defined(CPU_COLDFIRE)
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2004-10-26 05:40:24 +00:00
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.global memset
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.type memset,@function
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2004-03-18 22:06:36 +00:00
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2004-10-26 05:40:24 +00:00
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/* Fills a memory region with specified byte value
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2005-06-21 13:25:18 +00:00
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* This version is optimized for speed
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*
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* arguments:
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* (4,%sp) - start address
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* (8,%sp) - data
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* (12,%sp) - length
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*
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* return value:
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* %d0 - start address (like ANSI version)
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*
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* register usage:
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* %d0 - data (spread to all 4 bytes when using long stores)
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2005-06-21 18:15:35 +00:00
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* %d1 - temporary / data (for burst transfer)
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* %d2 - data (for burst transfer)
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* %d3 - data (for burst transfer)
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2005-06-21 13:25:18 +00:00
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* %a0 - start address
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* %a1 - current address (runs down from end to start)
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2005-06-21 18:15:35 +00:00
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*
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* For maximum speed this routine uses both long stores and burst mode,
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* storing whole lines with movem.l. The routine fills memory from end
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* to start in order to ease returning the start address.
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2004-10-26 05:40:24 +00:00
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*/
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memset:
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2005-06-21 13:25:18 +00:00
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move.l (4,%sp),%a0 /* start address */
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move.l (8,%sp),%d0 /* data */
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move.l (12,%sp),%a1 /* length */
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2005-06-21 18:15:35 +00:00
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add.l %a0,%a1 /* %a1 = end address */
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2005-06-21 13:25:18 +00:00
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move.l %a0,%d1
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2005-06-21 18:15:35 +00:00
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addq.l #7,%d1
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and.l #0xFFFFFFFC,%d1 /* %d1 = first long bound + 4 */
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2005-06-21 13:25:18 +00:00
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cmp.l %d1,%a1 /* at least one aligned longword to fill? */
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blo.b .no_longs /* no, jump directly to byte loop */
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and.l #0xFF,%d0 /* start: spread data to all 4 bytes */
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move.l %d0,%d1
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lsl.l #8,%d1
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or.l %d1,%d0 /* data now in 2 lower bytes of %d0 */
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move.l %d0,%d1
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swap %d0
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or.l %d1,%d0 /* data now in all 4 bytes of %d0 */
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2005-06-21 18:15:35 +00:00
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move.l %a1,%d1
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2005-06-21 13:25:18 +00:00
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and.l #0xFFFFFFFC,%d1 /* %d1 = last long bound */
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cmp.l %d1,%a1 /* any bytes to set? */
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bls.b .end_b1 /* no: skip byte loop */
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/* leading byte loop: sets 0..3 bytes */
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.loop_b1:
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move.b %d0,-(%a1) /* store byte */
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cmp.l %d1,%a1 /* runs %a1 down to last long bound */
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bhi.b .loop_b1
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.end_b1:
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2005-06-22 07:44:21 +00:00
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moveq.l #31,%d1
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add.l %a0,%d1
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2005-06-21 18:15:35 +00:00
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and.l #0xFFFFFFF0,%d1 /* %d1 = first line bound + 16 */
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cmp.l %d1,%a1 /* at least one full line to fill? */
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blo.b .no_lines /* no, jump to longword loop */
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mov.l %a1,%d1
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and.l #0xFFFFFFF0,%d1 /* %d1 = last line bound */
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cmp.l %d1,%a1 /* any longwords to set? */
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bls.b .end_l1 /* no: skip longword loop */
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/* leading longword loop: sets 0..3 longwords */
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.loop_l1:
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move.l %d0,-(%a1) /* store longword */
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cmp.l %d1,%a1 /* runs %a1 down to last line bound */
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bhi.b .loop_l1
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.end_l1:
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move.l %d2,-(%sp) /* free some registers */
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move.l %d3,-(%sp)
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2005-10-22 08:06:49 +00:00
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2005-06-21 18:15:35 +00:00
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move.l %d0,%d1 /* spread data to 4 data registers */
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move.l %d0,%d2
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move.l %d0,%d3
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2005-10-22 08:06:49 +00:00
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lea.l (15,%a0),%a0 /* start address += 15, acct. for trl. data */
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2005-06-21 18:15:35 +00:00
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/* main loop: set whole lines utilising burst mode */
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.loop_line:
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lea.l (-16,%a1),%a1 /* pre-decrement */
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movem.l %d0-%d3,(%a1) /* store line */
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2005-10-22 08:06:49 +00:00
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cmp.l %a0,%a1 /* runs %a1 down to first line bound */
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2005-06-21 18:15:35 +00:00
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bhi.b .loop_line
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2005-10-22 08:06:49 +00:00
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lea.l (-15,%a0),%a0 /* correct start address */
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move.l (%sp)+,%d3 /* restore registers */
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2005-06-21 18:15:35 +00:00
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move.l (%sp)+,%d2
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move.l %a0,%d1 /* %d1 = start address ... */
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addq.l #3,%d1 /* ... +3, account for possible trailing bytes */
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2005-10-22 08:06:49 +00:00
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cmp.l %d1,%a1 /* any longwords left */
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bhi.b .loop_l2 /* yes: jump to longword loop */
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bra.b .no_longs /* no: skip loop */
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2005-06-21 18:15:35 +00:00
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.no_lines:
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2005-06-21 13:25:18 +00:00
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move.l %a0,%d1 /* %d1 = start address ... */
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addq.l #3,%d1 /* ... +3, account for possible trailing bytes */
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2005-10-22 08:06:49 +00:00
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2005-06-21 18:15:35 +00:00
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/* trailing longword loop */
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.loop_l2:
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2005-06-21 13:25:18 +00:00
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move.l %d0,-(%a1) /* store longword */
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cmp.l %d1,%a1 /* runs %a1 down to first long bound */
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2005-06-21 18:15:35 +00:00
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bhi.b .loop_l2
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2005-06-21 13:25:18 +00:00
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.no_longs:
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cmp.l %a0,%a1 /* any bytes left? */
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bls.b .end_b2 /* no: skip loop */
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/* trailing byte loop */
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.loop_b2:
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move.b %d0,-(%a1) /* store byte */
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cmp.l %a0,%a1 /* runs %a1 down to start address */
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bhi.b .loop_b2
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.end_b2:
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move.l %a0,%d0 /* return start address */
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rts
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.end:
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.size memset,.end-memset
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2006-02-22 19:03:20 +00:00
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#elif defined(CPU_ARM)
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/* The following code is taken from the Linux kernel version 2.6.15.3
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* linux/arch/arm/lib/memset.S
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*
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* Copyright (C) 1995-2000 Russell King
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*/
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@ .word 0
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1: subs r2, r2, #4 @ 1 do we have enough
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blt 5f @ 1 bytes to align with?
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cmp r3, #2 @ 1
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strltb r1, [r0], #1 @ 1
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strleb r1, [r0], #1 @ 1
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strb r1, [r0], #1 @ 1
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add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
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/*
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* The pointer is now aligned and the length is adjusted. Try doing the
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* memzero again.
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*/
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.global memset
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.type memset,%function
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memset:
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ands r3, r0, #3 @ 1 unaligned?
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bne 1b @ 1
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/*
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* we know that the pointer in r0 is aligned to a word boundary.
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*/
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orr r1, r1, r1, lsl #8
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orr r1, r1, r1, lsl #16
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mov r3, r1
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cmp r2, #16
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blt 4f
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/*
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* We need an extra register for this loop - save the return address and
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* use the LR
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*/
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str lr, [sp, #-4]!
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mov ip, r1
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mov lr, r1
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2: subs r2, r2, #64
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stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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bgt 2b
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ldmeqfd sp!, {pc} @ Now <64 bytes to go.
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/*
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* No need to correct the count; we're only testing bits from now on
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*/
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tst r2, #32
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stmneia r0!, {r1, r3, ip, lr}
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stmneia r0!, {r1, r3, ip, lr}
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tst r2, #16
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stmneia r0!, {r1, r3, ip, lr}
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ldr lr, [sp], #4
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4: tst r2, #8
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stmneia r0!, {r1, r3}
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tst r2, #4
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strne r1, [r0], #4
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/*
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* When we get here, we've got less than 4 bytes to zero. We
|
|
|
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* may have an unaligned pointer as well.
|
|
|
|
*/
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|
|
|
5: tst r2, #2
|
|
|
|
strneb r1, [r0], #1
|
|
|
|
strneb r1, [r0], #1
|
|
|
|
tst r2, #1
|
|
|
|
strneb r1, [r0], #1
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|
|
|
mov pc, lr
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|
end:
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.size memset,.end-memset
|
2004-10-26 05:40:24 +00:00
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#endif
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2006-02-22 19:03:20 +00:00
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