2009-10-20 06:37:07 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "usb.h"
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2010-08-08 10:49:32 +00:00
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#include "usb-target.h"
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#include "usb_drv.h"
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2009-10-20 06:37:07 +00:00
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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2010-12-12 00:52:02 +00:00
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#include "usb-s3c6400x.h"
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2009-10-20 06:37:07 +00:00
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#ifdef HAVE_USBSTACK
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#include "usb_ch9.h"
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#include "usb_core.h"
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#include <inttypes.h>
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#include "power.h"
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struct ep_type
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{
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bool active;
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bool busy;
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bool done;
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int rc;
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int size;
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2011-03-02 08:49:38 +00:00
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struct semaphore complete;
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2009-10-20 06:37:07 +00:00
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} ;
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2010-09-08 03:31:11 +00:00
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static struct ep_type endpoints[USB_NUM_ENDPOINTS];
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2011-11-10 10:37:02 +00:00
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/* USB control requests may be up to 64 bytes in size.
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Even though we never use anything more than the 8 header bytes,
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we are required to accept request packets of up to 64 bytes size.
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Provide buffer space for these additional payload bytes so that
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e.g. write descriptor requests (which are rejected by us, but the
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payload is transferred anyway) do not cause memory corruption.
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Fixes FS#12310. -- Michael Sparmann (theseven) */
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static struct
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2011-11-06 00:56:26 +00:00
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{
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2011-11-10 10:37:02 +00:00
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struct usb_ctrlrequest header; /* 8 bytes */
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unsigned char payload[64 - sizeof(struct usb_ctrlrequest)];
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2011-11-06 00:56:26 +00:00
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} ctrlreq USB_DEVBSS_ATTR;
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2009-10-20 06:37:07 +00:00
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int usb_drv_port_speed(void)
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{
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return (DSTS & 2) == 0 ? 1 : 0;
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}
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2010-08-08 10:49:32 +00:00
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static void reset_endpoints(int reinit)
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2009-10-20 06:37:07 +00:00
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{
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unsigned int i;
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for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
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{
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if (reinit) endpoints[i].active = false;
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endpoints[i].busy = false;
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endpoints[i].rc = -1;
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endpoints[i].done = true;
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2011-03-02 08:49:38 +00:00
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semaphore_release(&endpoints[i].complete);
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2009-10-20 06:37:07 +00:00
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}
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2011-12-13 05:13:22 +00:00
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DIEPCTL(0) = DEPCTL_usbactep | (1 << DEPCTL_nextep_bitp);
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DOEPCTL(0) = DEPCTL_usbactep;
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DOEPTSIZ(0) = (1 << DEPTSIZ_pkcnt_bitp) | (1 << DEPTSIZ0_supcnt_bitp) | 64;
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2011-12-13 04:21:06 +00:00
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DOEPDMA(0) = &ctrlreq;
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2011-12-13 05:13:22 +00:00
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DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak;
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2009-10-20 06:37:07 +00:00
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if (reinit)
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{
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/* The size is getting set to zero, because we don't know
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whether we are Full Speed or High Speed at this stage */
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2011-12-13 05:13:22 +00:00
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DIEPCTL(1) = DEPCTL_setd0pid | (3 << DEPCTL_nextep_bitp);
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DOEPCTL(2) = DEPCTL_setd0pid;
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DIEPCTL(3) = DEPCTL_setd0pid | (0 << DEPCTL_nextep_bitp);
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DOEPCTL(4) = DEPCTL_setd0pid;
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2009-10-20 06:37:07 +00:00
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}
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else
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{
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2011-12-13 05:13:22 +00:00
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DIEPCTL(1) = (DIEPCTL(1) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DOEPCTL(2) = (DOEPCTL(2) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DIEPCTL(3) = (DIEPCTL(3) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DOEPCTL(4) = (DOEPCTL(4) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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2009-10-20 06:37:07 +00:00
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}
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */
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}
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int usb_drv_request_endpoint(int type, int dir)
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{
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size_t ep;
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int ret = -1;
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if (dir == USB_DIR_IN) ep = 1;
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else ep = 2;
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2010-09-08 03:31:11 +00:00
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while (ep < USB_NUM_ENDPOINTS)
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2009-10-20 06:37:07 +00:00
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{
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if (!endpoints[ep].active)
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{
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endpoints[ep].active = true;
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ret = ep | dir;
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2011-12-13 05:13:22 +00:00
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uint32_t newbits = (type << DEPCTL_eptype_bitp) | DEPCTL_epena;
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uint32_t mask = DEPCTL_eptype_bits << DEPCTL_eptype_bitp;
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if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~mask) | newbits;
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else DOEPCTL(ep) = (DOEPCTL(ep) & ~mask) | newbits;
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2009-10-20 06:37:07 +00:00
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break;
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}
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ep += 2;
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}
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return ret;
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}
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void usb_drv_release_endpoint(int ep)
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{
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ep = ep & 0x7f;
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if (ep < 1 || ep > USB_NUM_ENDPOINTS) return;
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endpoints[ep].active = false;
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}
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static void usb_reset(void)
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{
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2011-12-13 05:13:22 +00:00
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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2009-10-20 06:37:07 +00:00
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OPHYPWR = 0; /* PHY: Power up */
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2011-11-06 00:04:52 +00:00
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udelay(10);
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2010-12-12 00:52:02 +00:00
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OPHYUNK1 = 1;
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OPHYUNK2 = 0xE3F;
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2009-10-20 06:37:07 +00:00
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ORSTCON = 1; /* PHY: Assert Software Reset */
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2011-11-06 00:04:52 +00:00
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udelay(10);
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2009-10-20 06:37:07 +00:00
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ORSTCON = 0; /* PHY: Deassert Software Reset */
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2010-12-12 00:52:02 +00:00
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OPHYUNK3 = 0x600;
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2011-11-06 00:04:52 +00:00
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OPHYCLK = SYNOPSYSOTG_CLOCK;
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udelay(400);
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2009-10-20 06:37:07 +00:00
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2011-12-13 05:13:22 +00:00
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GRSTCTL = GRSTCTL_csftrst; /* OTG: Assert Software Reset */
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while (GRSTCTL & GRSTCTL_csftrst); /* Wait for OTG to ack reset */
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while (!(GRSTCTL & GRSTCTL_ahbidle)); /* Wait for OTG AHB master idle */
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GRXFSIZ = 512;
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GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512);
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2009-10-20 06:37:07 +00:00
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2010-12-12 00:52:02 +00:00
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GAHBCFG = SYNOPSYSOTG_AHBCFG;
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2011-12-13 05:13:22 +00:00
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GUSBCFG = (1 << 12) | (1 << 10) | GUSBCFG_phy_if; /* OTG: 16bit PHY and some reserved bits */
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2009-10-20 06:37:07 +00:00
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2011-12-13 05:13:22 +00:00
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DCFG = DCFG_nzstsouthshk; /* Address 0 */
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DCTL = DCTL_pwronprgdone; /* Soft Reconnect */
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DIEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl;
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DOEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl;
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2010-08-12 08:35:43 +00:00
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */
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2011-12-13 05:13:22 +00:00
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GINTMSK = GINTMSK_outepintr | GINTMSK_inepintr | GINTMSK_usbreset | GINTMSK_enumdone;
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2009-10-20 06:37:07 +00:00
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reset_endpoints(1);
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}
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/* IRQ handler */
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void INT_USB_FUNC(void)
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{
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int i;
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2010-08-12 08:35:43 +00:00
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uint32_t ints = GINTSTS;
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uint32_t epints;
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2011-12-13 05:13:22 +00:00
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if (ints & GINTMSK_usbreset)
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2009-10-20 06:37:07 +00:00
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{
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2011-12-13 05:13:22 +00:00
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DCFG = DCFG_nzstsouthshk; /* Address 0 */
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2009-10-20 06:37:07 +00:00
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reset_endpoints(1);
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usb_core_bus_reset();
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}
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2011-12-13 05:13:22 +00:00
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if (ints & GINTMSK_enumdone) /* enumeration done, we now know the speed */
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2009-10-20 06:37:07 +00:00
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{
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/* Set up the maximum packet sizes accordingly */
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2011-12-13 05:13:22 +00:00
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uint32_t maxpacket = (usb_drv_port_speed() ? 512 : 64) << DEPCTL_mps_bitp;
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DIEPCTL(1) = (DIEPCTL(1) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DOEPCTL(2) = (DOEPCTL(2) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DIEPCTL(3) = (DIEPCTL(3) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DOEPCTL(4) = (DOEPCTL(4) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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2009-10-20 06:37:07 +00:00
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}
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2011-12-13 05:13:22 +00:00
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if (ints & GINTMSK_inepintr)
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2010-08-12 08:35:43 +00:00
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for (i = 0; i < 4; i += i + 1) // 0, 1, 3
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if ((epints = DIEPINT(i)))
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2009-10-20 06:37:07 +00:00
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{
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_xfercompl)
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2009-10-20 06:37:07 +00:00
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{
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invalidate_dcache();
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int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 0;
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endpoints[i].done = true;
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usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes);
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2011-03-02 08:49:38 +00:00
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semaphore_release(&endpoints[i].complete);
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2009-10-20 06:37:07 +00:00
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}
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}
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_ahberr)
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2009-10-20 06:37:07 +00:00
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panicf("USB: AHB error on IN EP%d", i);
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_timeout)
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2009-10-20 06:37:07 +00:00
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{
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 1;
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endpoints[i].done = true;
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2011-03-02 08:49:38 +00:00
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semaphore_release(&endpoints[i].complete);
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2009-10-20 06:37:07 +00:00
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}
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}
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2010-08-12 08:35:43 +00:00
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DIEPINT(i) = epints;
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2009-10-20 06:37:07 +00:00
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}
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2011-12-13 05:13:22 +00:00
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if (ints & GINTMSK_outepintr)
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2010-09-08 03:31:11 +00:00
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for (i = 0; i < USB_NUM_ENDPOINTS; i += 2)
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2010-08-12 08:35:43 +00:00
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if ((epints = DOEPINT(i)))
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2009-10-20 06:37:07 +00:00
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{
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_xfercompl)
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2009-10-20 06:37:07 +00:00
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{
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invalidate_dcache();
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2011-12-13 05:13:22 +00:00
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int bytes = endpoints[i].size - (DOEPTSIZ(i) & (DEPTSIZ_xfersize_bits < DEPTSIZ_xfersize_bitp));
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2009-10-20 06:37:07 +00:00
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 0;
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endpoints[i].done = true;
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usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes);
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2011-03-02 08:49:38 +00:00
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semaphore_release(&endpoints[i].complete);
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2009-10-20 06:37:07 +00:00
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}
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}
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_ahberr)
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2009-10-20 06:37:07 +00:00
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panicf("USB: AHB error on OUT EP%d", i);
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2011-12-13 05:13:22 +00:00
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if (epints & DIEPINT_timeout) /* SETUP phase done */
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2009-10-20 06:37:07 +00:00
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{
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invalidate_dcache();
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if (i == 0)
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{
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2011-11-10 10:37:02 +00:00
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if (ctrlreq.header.bRequest == 5)
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2009-10-20 06:37:07 +00:00
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{
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/* Already set the new address here,
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before passing the packet to the core.
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See below (usb_drv_set_address) for details. */
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2011-12-13 05:13:22 +00:00
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DCFG = (DCFG & ~(DCFG_devadr_bits << DCFG_devadr_bitp)) | (ctrlreq.header.wValue << DCFG_devadr_bitp);
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2009-10-20 06:37:07 +00:00
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}
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2011-11-10 10:37:02 +00:00
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usb_core_control_request(&ctrlreq.header);
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2009-10-20 06:37:07 +00:00
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}
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else panicf("USB: SETUP done on OUT EP%d!?", i);
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}
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/* Make sure EP0 OUT is set up to accept the next request */
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2011-12-13 05:13:22 +00:00
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if (i == 0)
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2009-10-20 06:37:07 +00:00
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{
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2011-12-13 05:13:22 +00:00
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DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp) | (1 << DEPTSIZ0_pkcnt_bitp) | 64;
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2011-12-13 04:21:06 +00:00
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DOEPDMA(0) = &ctrlreq;
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2011-12-13 05:13:22 +00:00
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DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak;
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2009-10-20 06:37:07 +00:00
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}
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2010-08-12 08:35:43 +00:00
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DOEPINT(i) = epints;
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2009-10-20 06:37:07 +00:00
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}
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2010-08-12 08:35:43 +00:00
|
|
|
GINTSTS = ints;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_set_address(int address)
|
|
|
|
{
|
|
|
|
(void)address;
|
|
|
|
/* Ignored intentionally, because the controller requires us to set the
|
|
|
|
new address before sending the response for some reason. So we'll
|
|
|
|
already set it when the control request arrives, before passing that
|
|
|
|
into the USB core, which will then call this dummy function. */
|
|
|
|
}
|
|
|
|
|
2010-08-12 08:35:43 +00:00
|
|
|
static void ep_send(int ep, const void *ptr, int length)
|
2009-10-20 06:37:07 +00:00
|
|
|
{
|
|
|
|
endpoints[ep].busy = true;
|
|
|
|
endpoints[ep].size = length;
|
2011-12-13 05:13:22 +00:00
|
|
|
DIEPCTL(ep) |= DEPCTL_usbactep;
|
2009-10-20 06:37:07 +00:00
|
|
|
int blocksize = usb_drv_port_speed() ? 512 : 64;
|
|
|
|
int packets = (length + blocksize - 1) / blocksize;
|
2010-01-17 19:05:42 +00:00
|
|
|
if (!length)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DIEPTSIZ(ep) = 1 << DEPTSIZ0_pkcnt_bitp; /* one empty packet */
|
2010-12-12 00:59:59 +00:00
|
|
|
DIEPDMA(ep) = NULL;
|
2010-01-17 19:05:42 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DIEPTSIZ(ep) = length | (packets << DEPTSIZ0_pkcnt_bitp);
|
2010-12-12 00:59:59 +00:00
|
|
|
DIEPDMA(ep) = ptr;
|
2010-01-17 19:05:42 +00:00
|
|
|
}
|
2009-10-20 06:37:07 +00:00
|
|
|
clean_dcache();
|
2011-12-13 05:13:22 +00:00
|
|
|
DIEPCTL(ep) |= DEPCTL_epena | DEPCTL_cnak;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
2010-08-08 10:49:32 +00:00
|
|
|
static void ep_recv(int ep, void *ptr, int length)
|
2009-10-20 06:37:07 +00:00
|
|
|
{
|
|
|
|
endpoints[ep].busy = true;
|
|
|
|
endpoints[ep].size = length;
|
2011-12-13 05:13:22 +00:00
|
|
|
DOEPCTL(ep) &= ~DEPCTL_naksts;
|
|
|
|
DOEPCTL(ep) |= DEPCTL_usbactep;
|
2009-10-20 06:37:07 +00:00
|
|
|
int blocksize = usb_drv_port_speed() ? 512 : 64;
|
|
|
|
int packets = (length + blocksize - 1) / blocksize;
|
2010-01-17 19:05:42 +00:00
|
|
|
if (!length)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DOEPTSIZ(ep) = 1 << DEPTSIZ0_pkcnt_bitp; /* one empty packet */
|
2010-12-12 00:59:59 +00:00
|
|
|
DOEPDMA(ep) = NULL;
|
2010-01-17 19:05:42 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DOEPTSIZ(ep) = length | (packets << DEPTSIZ0_pkcnt_bitp);
|
2010-12-12 00:59:59 +00:00
|
|
|
DOEPDMA(ep) = ptr;
|
2010-01-17 19:05:42 +00:00
|
|
|
}
|
2009-10-20 06:37:07 +00:00
|
|
|
clean_dcache();
|
2011-12-13 05:13:22 +00:00
|
|
|
DOEPCTL(ep) |= DEPCTL_epena | DEPCTL_cnak;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
2010-08-12 08:43:18 +00:00
|
|
|
int usb_drv_send(int endpoint, void *ptr, int length)
|
2009-10-20 06:37:07 +00:00
|
|
|
{
|
|
|
|
endpoint &= 0x7f;
|
|
|
|
endpoints[endpoint].done = false;
|
|
|
|
ep_send(endpoint, ptr, length);
|
|
|
|
while (!endpoints[endpoint].done && endpoints[endpoint].busy)
|
2011-03-02 08:49:38 +00:00
|
|
|
semaphore_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);
|
2009-10-20 06:37:07 +00:00
|
|
|
return endpoints[endpoint].rc;
|
|
|
|
}
|
|
|
|
|
2010-08-12 08:43:18 +00:00
|
|
|
int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
|
2009-10-20 06:37:07 +00:00
|
|
|
{
|
|
|
|
ep_send(endpoint & 0x7f, ptr, length);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int usb_drv_recv(int endpoint, void* ptr, int length)
|
|
|
|
{
|
|
|
|
ep_recv(endpoint & 0x7f, ptr, length);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_cancel_all_transfers(void)
|
|
|
|
{
|
|
|
|
int flags = disable_irq_save();
|
|
|
|
reset_endpoints(0);
|
|
|
|
restore_irq(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_set_test_mode(int mode)
|
|
|
|
{
|
|
|
|
(void)mode;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool usb_drv_stalled(int endpoint, bool in)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
if (in) return DIEPCTL(endpoint) & DEPCTL_naksts;
|
|
|
|
else return DOEPCTL(endpoint) & DEPCTL_naksts;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_stall(int endpoint, bool stall, bool in)
|
|
|
|
{
|
|
|
|
if (in)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
if (stall) DIEPCTL(endpoint) |= DEPCTL_naksts;
|
|
|
|
else DIEPCTL(endpoint) &= ~DEPCTL_naksts;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
if (stall) DOEPCTL(endpoint) |= DEPCTL_naksts;
|
|
|
|
else DOEPCTL(endpoint) &= ~DEPCTL_naksts;
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_init(void)
|
|
|
|
{
|
|
|
|
/* Enable USB clock */
|
2010-12-12 00:52:02 +00:00
|
|
|
#if CONFIG_CPU==S5L8701
|
2009-10-20 06:37:07 +00:00
|
|
|
PWRCON &= ~0x4000;
|
|
|
|
PWRCONEXT &= ~0x800;
|
|
|
|
INTMSK |= INTMSK_USB_OTG;
|
2010-12-12 00:52:02 +00:00
|
|
|
#elif CONFIG_CPU==S5L8702
|
|
|
|
PWRCON(0) &= ~0x4;
|
|
|
|
PWRCON(1) &= ~0x8;
|
|
|
|
VIC0INTENABLE |= 1 << 19;
|
|
|
|
#endif
|
|
|
|
PCGCCTL = 0;
|
2009-10-20 06:37:07 +00:00
|
|
|
|
|
|
|
/* reset the beast */
|
|
|
|
usb_reset();
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_drv_exit(void)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
|
2009-10-20 06:37:07 +00:00
|
|
|
|
|
|
|
OPHYPWR = 0xF; /* PHY: Power down */
|
2011-11-06 00:04:52 +00:00
|
|
|
udelay(10);
|
|
|
|
ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
|
|
|
|
udelay(10);
|
|
|
|
PCGCCTL = 1; /* Shut down PHY clock */
|
2009-10-20 06:37:07 +00:00
|
|
|
|
2010-12-12 00:52:02 +00:00
|
|
|
#if CONFIG_CPU==S5L8701
|
2009-10-20 06:37:07 +00:00
|
|
|
PWRCON |= 0x4000;
|
|
|
|
PWRCONEXT |= 0x800;
|
2010-12-12 00:52:02 +00:00
|
|
|
#elif CONFIG_CPU==S5L8702
|
|
|
|
PWRCON(0) |= 0x4;
|
|
|
|
PWRCON(1) |= 0x8;
|
|
|
|
#endif
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void usb_init_device(void)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
|
2011-03-02 08:49:38 +00:00
|
|
|
semaphore_init(&endpoints[i].complete, 1, 0);
|
2010-10-12 23:14:27 +00:00
|
|
|
|
|
|
|
/* Power up the core clocks to allow writing
|
|
|
|
to some registers needed to power it down */
|
2010-12-12 00:52:02 +00:00
|
|
|
PCGCCTL = 0;
|
|
|
|
#if CONFIG_CPU==S5L8701
|
2010-10-12 23:14:27 +00:00
|
|
|
PWRCON &= ~0x4000;
|
|
|
|
PWRCONEXT &= ~0x800;
|
|
|
|
INTMSK |= INTMSK_USB_OTG;
|
2010-12-12 00:52:02 +00:00
|
|
|
#elif CONFIG_CPU==S5L8702
|
|
|
|
PWRCON(0) &= ~0x4;
|
|
|
|
PWRCON(1) &= ~0x8;
|
|
|
|
VIC0INTENABLE |= 1 << 19;
|
|
|
|
#endif
|
2010-10-12 23:14:27 +00:00
|
|
|
|
2009-10-20 06:37:07 +00:00
|
|
|
usb_drv_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_enable(bool on)
|
|
|
|
{
|
|
|
|
if (on) usb_core_init();
|
|
|
|
else usb_core_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
void usb_attach(void)
|
|
|
|
{
|
|
|
|
usb_enable(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
int usb_detect(void)
|
|
|
|
{
|
|
|
|
if (charger_inserted())
|
|
|
|
return USB_INSERTED;
|
|
|
|
return USB_EXTRACTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
void usb_init_device(void)
|
|
|
|
{
|
2011-12-13 05:13:22 +00:00
|
|
|
DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
|
2009-10-20 06:37:07 +00:00
|
|
|
|
2009-10-24 20:31:40 +00:00
|
|
|
ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
|
|
|
|
PCGCCTL = 1; /* Shut down PHY clock */
|
2009-10-20 06:37:07 +00:00
|
|
|
OPHYPWR = 0xF; /* PHY: Power down */
|
|
|
|
|
2010-12-12 00:52:02 +00:00
|
|
|
#if CONFIG_CPU==S5L8701
|
2009-10-20 06:37:07 +00:00
|
|
|
PWRCON |= 0x4000;
|
|
|
|
PWRCONEXT |= 0x800;
|
2010-12-12 00:52:02 +00:00
|
|
|
#elif CONFIG_CPU==S5L8702
|
|
|
|
PWRCON(0) |= 0x4;
|
|
|
|
PWRCON(1) |= 0x8;
|
|
|
|
#endif
|
2009-10-20 06:37:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void usb_enable(bool on)
|
|
|
|
{
|
|
|
|
(void)on;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Always return false for now */
|
|
|
|
int usb_detect(void)
|
|
|
|
{
|
|
|
|
return USB_EXTRACTED;
|
|
|
|
}
|
|
|
|
#endif
|